TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 50

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

7 Clock/Mode Control
7.3
7.3.1
7.3.2
For example, reset configures fsys as 10MHz when a 10MHz oscillator is connected to the X1 or X2 pin.
Fig.7-1 shows the clock system diagram. Each clock is defined as follows.
The high-speed clock fc and the prescaler clock ΦT0 are dividable.
•
•
Reset initializes the clock configuration as follows.
Reset causes all the clock configurations excluding the low-speed clock (fs) to be the same as fosc.
Clock Control
fosc
fs
fpll
fc
fgear
fsys
fperiph : Clock specified by SYSCR1<FPSEL2:0>
ΦT0
High-speed clock: fc, fc/2, fc/4, fc/8
Prescaler clock: fperiph, fperiph/2, fperiph/4, fperiph/8, fperiph/16,fperiph/32
High-speed oscillator
Low-speed oscillator
PLL (phase locked loop circuit)
High-speed clock gear
Clock System Block Diagram
Initial Values after Reset
: Clock input from the X1 and X2 pins
: Clock input from the XT1 and XT2 (low-speed clock)
: Clock quadrupled by PLL
: Clock specified by PLLSEL<PLLSEL> (high-speed clock)
: Clock specified by SYSCR1<GEAR2:0>
: Clock specified by CKSEL<SYSCK> (system clock)
: Clock specified by SYSCR1<PRCK2:0> (prescaler clock)
Under development
: ON (oscillating)
: ON (oscillating)
: OFF (stop)
: fc (no frequency dividing)
Page38
TMPM330