TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 419

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12. The 27th to mth bytes from the controller are stored in the on-chip RAM of the
13. The (m+1) th byte is a checksum value. To calculate the checksum value, add the 27th
14. The (m+2) th byte is a acknowledge response to the 27th to (m+1) th bytes.
15. If the (m+2) th byte was a normal acknowledge response, a branch is made to the
Next, the RAM Transfer routine performs the checksum operation to ensure data
integrity. Adding the series of the 19th to 25th bytes must result in 00H (with the carry
dropped). If it is not 00H, one or more bytes of data has been corrupted. In case of a
checksum error, the RAM Transfer routine sends back 11H to the controller and returns
to the state in which it waits for a command (i.e., the 3rd byte) again.
TMPM330. Storage begins at the address specified by the 19th–22nd bytes and
continues for the number of bytes specified by the 23rd–24th bytes.
to mth bytes together, drop the carries and take the two’s complement of the total sum.
Transmit this checksum value from the controller to the target board. The checksum
calculation is described in details in a later section “Checksum Calculation”.
address specified by the 19th to 22nd bytes.
If there was a receive error, the RAM Transfer routine sends back 18H (bit 3) and
returns to the state in which it waits for a command (i.e., the 3rd byte) again. In this
case, the upper four bits of the acknowledge response are the same as those of the
previously issued command (i.e., all 1s). When the SIO0 is configured for I/O Interface
mode, the RAM Transfer routine does not check for a receive error.
Next, the RAM Transfer routine performs the checksum operation to ensure data
integrity. Adding the series of the 27th to (m+1) th bytes must result in 00H (with the
carry dropped). If it is not 00H, one or more bytes of data has been corrupted. In case
of a checksum error, the RAM Transfer routine sends back 11H (bit 0) to the controller
and returns to the command wait state (i.e., the 3rd byte) again. When the above
checks have been successful, the RAM Transfer routine returns a normal
acknowledge response (10H) to the controller.
• The RAM storage start address must be within the range of 0x2000_0400 to the
When the above checks have been successful, the RAM Transfer routine returns a
normal acknowledge response (10H) to the controller.
First, the RAM Transfer routine checks for a receive error in the 27th to (m+1) th bytes.
end address of RAM.
Under development
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TMPM330