M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 85

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
M
R
R
e
E
3
. v
J
2
Table 8.2 Processor Mode and Port Function
Data Bus Width
NOTES:
0
C
PM0 Register
P0
P1
P2
P3
P4
P4
P4
P5
P5
P5
P5
P5
PM04 Bits in
1
Processor
9
0 .
8 /
B
PM05 to
1. The PM05 and PM04 bits cannot be set to "11
2. These ports become address buses when accessing space using the separate bus.
3. The PM15 and PM14 bits in the PM1 register determines which pin outputs the ALE signal. The PM02 bit in the PM0
4. The PM11 and PM10 bits in the PM1 register determine the CS signal and address bus.
Mode
0
0
0
0
0
4
7
0
4
5
6
7
0
1
4
to P0
to P1
to P2
to P3
to P4
to P4
to P5
because the microcomputer starts operation using the separate bus after reset.
When the PM05 and PM04 bits are set to "11
memory space per chip-select using the address bus .
register selects either "WRL,WRH" or "BHE,WR" combination.
P5
0
3
G
J
6
6
u
o r
0 -
provides an indeterminate output when the PM15 and PM14 bits to "002" (no ALE). It cannot be used as an I/O port.
. l
7
7
7
7
3
6
3
u
0
1
p
, 7
0
Chip Mode
1
(
2
M
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
Single-
0
3
0
5
2
C
8 /
Page 62
, 4
external space with
Access All Other CS Areas using
CS (Chip-select signal) or Address bus (A
Address bus
Data bus
A
CS (Chip-select signal) or Address bus (A
Outputs RD, WRL, WRH and BCLK or outputs RD, BHE, WR and BCLK
M
8-bit data bus
Address bus
Address bus
0
Data bus
/D
HDLA
Access all
A
ALE
3
A
Access CS1 or CS2 using
D
I/O port
HOLD
16
RDY
0
8
2
0
to
to
the Multiplexed Bus
to
C
to
the Separate Bus
(Refer to 8.2 Bus Control for details)
A
A
(3)
D
f o
8 /
A
(2)
Memory Expansion Mode/ Microprocessor Mode
"01
15
(3)
7
7
19
/D
4
4
) T
2
7
9
", "10
5
Access one or more
external space with
Address bus/
Data bus
A
(Refer to 8.2 Bus Control for details)
Address bus
Data bus
A
16-bit data bus
8
Address bus
2
0
/D
Data bus
/D
A
"
Data bus
HDLA
D
D
ALE
8
16
HOLD
8
0
RDY
0
to
to
to
2
to
to
2
" in memory expansion mode, the microcomputer accesses 64-Kbyte
A
(2)
" (access all CS areas using multiplexed bus) in microprocessor mode
D
A
D
A
(Refer to 8.2 Bus Control for details)
(3)
(2)
15
7
15
19
(3)
7
/D
/D
7
15
external space with
Address bus
Address bus
Address bus
8-bit data bus
A
A
Data bus
Access all
HDLA
A
I/O port
ALE
D
Access all CS Areas using
16
8
HOLD
0
RDY
0
to
to
to
to
A
the Separate Bus
A
A
(3)
D
15
23
7
20
19
(3)
7
(3)
)
to A
"00
Access one or more
22
2
external space with
"
16-bit data bus
Address bus
)
Address bus
Address bus
Data bus
A
Data bus
D
(4)
HDLA
A
D
16
ALE
A
8
HOLD
8
0
RDY
0
to
to
to
to
to
D
A
A
D
(3)
A
15
19
15
(3)
7
7
(4)
external space with
Address bus
Data bus
A
Address bus
0
8-bit data bus
/D
Memory Expansion Mode
A
HDLA
Access all
I/O port
I/O port
I/O port
ALE
Access all CS Areas using
8
HOLD
0
RDY
to
to
the Multiplexed Bus
A
A
(3)
15
7
(3)
/D
7
"11
Access one or more
Address bus/
Data bus
A
external space with
2
Address bus
Data bus
A
"
8
16-bit data bus
(1)
/D
0
/D
HDLA
8
ALE
I/O port
I/O port
I/O port
HOLD
0
to
RDY
to
A
A
15
(3)
7
(3)
/D
/D
15
7
8. Bus