M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 118

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
M
R
R
9.2 CPU Clock and BCLK
9.3 Peripheral Function Clock
e
E
3
. v
J
2
Table 9.4 CPU Clock Source and Bit Settings
0
NOTES:
C
M
M
P
The CPU operating clock is referred to as the CPU clock. The CPU clock is also a count source for the
watchdog timer. After reset, the CPU clock is the main clock divided-by-8 . In memory expansion or micro-
processor mode, the clock having the same frequency as the CPU clock can be output from the BCLK pin
as BCLK. Refer to 9.4 Clock Output Function for details.
The main clock, sub clock, on-chip oscillator clock or PLL clock can be selected as a clock source for the
CPU clock. Table 9.4 shows CPU clock source and bit settings.
When the main clock, on-chip oscillator clock or PLL clock is selected as a clock source of the CPU clock,
the selected clock divided-by-1 (no division), -2, -3, -4, -6, -8, -10, -12, -14 or -16 becomes the CPU clock.
The MCD4 to MCD0 bits in the MCD register select the clock division.
When the microcomputer enters stop mode or low-power consumption mode (except when the on-chip
oscillator clock is the CPU clock), the MCD4 to MCD0 bits are set to "01000
fore, when the main clock starts running, the CPU clock enters medium-speed mode (divide-by-8).
S
O
The peripheral function clock becomes an operating clock or count source for peripheral functions exclud-
ing the watchdog timer.
9.3.1 f
9.3.2 f
1
9
8 /
u
L
0 .
a
a
- n
B
f
PM27 and PM26 bits in the PM2 register selects a f
and the on-chip oscillator clock. The CNT3 to CNT0 bits in the TCSPR register selects a f
to 15. No division when n=0.)
f
to enter wait mode or when in low-power consumption mode.
f
also used as an operating clock for the intelligent I/O.
The CLK
f
the on-chip oscillator clock. The CM21 bit determines which clock is selected.
If the CM02 bit is set to "1" (peripheral function stop in wait mode) to enter wait mode, f
stops in low-power consumption mode.
NOTES:
L
b
1. Refer to 23.2 CAN Clock for details.
1
1
1
AD
n i
n i
0
1
4
C
, f
, f
, f
0
C
C
1. The PLL clock, instead of the main clock, when the CM17 bit is set to "1" (PLL clock).
C
C
h
G
3
8
8
J
o l
o l
8
is an operating clock for the A/D converter and has the same frequency as either the main clock
p i
6
o l
o l
, f
u
o r
and f
k c
k c
and f
0 -
. l
k c
k c
32
O
1
AD
u
0
1
c s
, f
p
, 7
0
(
and f
OUT
M
1
l l i
(
2n
8
32
2
M
C
a
t a
, f
0
n i
P
3
are used as an operating clock of the serial I/O and count source of the timers A and B. f
r o
0
are the peripheral function clock, selected by the CM21 bit, divided-by-1, -8, or -32. The
pin outputs f
2n
32
U
2
5
C
C
C
o l
C
stop when the CM02 bit in the CM0 register to "1" (peripheral function stops in wait mode)
o l
8 /
and f
o l
k c
Page 95
k c
, 4
k c
i D
M
S
e r
o
3
2n
t c
u
2
c r
C
8
M
e
8 /
and f
f o
o
d
4
4
) e
) T
9
(
5
) 1
32
. Refer to 9.4 Clock Output Function for details.
C
M
C
0
M
R
0
0
0
0
0
1
e
7
g
B
2n
t s i
t i
r e
count source from the peripheral clock, X
C
M
C
1
M
R
1
0
0
0
0
1
7
e
g
B
t s i
t i
r e
C
M
2
C
" (divide-by-8 mode). There-
2
M
R
2
0
0
0
0
1
e
1
9. Clock Generation Circuit
g
B
t s i
t i
r e
AD
P
2n
M
stops. f
P
2
M
division. (n=1
R
2
0
0
0
0
1
e
4
g
B
t s i
IN
t i
AD
r e
clock,
(1)
also
1
or
is