M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 338

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
M
R
R
e
E
3
. v
J
2
n
NOTES:
NOTES:
Table 22.21 Clock Settings (Communication Unit 1)
Table 22.22 Register Settings in UART Mode (Communication Unit 1)
Table 22.23 Pin Settings in UART Mode
0
C
Transfer Clock
: Value of the G1PO0 register 0001
G1BCR0
G1BCR1
G1POCR0
G1POCR2
G1POCR3
G1TMCR2
G1PO0
G1PO3
G1FS
G1FE
G1MR
G1CR
G1TB
G1RB
CCS
Name
P7
P7
1
9
Port
1. Transmit clock is generated in phase-delayed waveform output mode of the channel 3 waveform
2. Received clock is generated when phase-delayed waveform mode of the channel 2 waveform gener-
3. The transfer clock must be f
1. Set the MOD2 to MOD0 bits in the corresponding register to "111
0 .
8 /
B
Register
3
5
0
1
4
generating function.
ating function and the channel 2 time measurement function is simultaneously performed.
used).
0
3
G
J
6
u
2(
o r
0 -
fBT1
. l
ISTxD1 output
ISRxD1 input
n
u
0
1
+2)
p
, 7
0
Function
1
(
2
M
(3)
(1, 2)
0
3
0
BCK1, BCK0
DIV4 to DIV0
IT
7 to 0
7 to 0
7 to 0
7 to 0
7 to 0
15 to 0
15 to 0
FSC3 to FSC0
IFE3 to IFE0
GMD1, GMD0
CKDIR
STPS
PRY, PRYE
UFORM
IRS
TI
TXEPT
RI
TE
RE
IPOL
OPOL
7 to 0
15 to 0
CCS3, CCS2
2
5
C
8 /
Page 315
G1MR Register
, 4
Bit
PS1 Register PSL1 Register PSC Register PD7 Register IPS Register
PS1_3 = 1
PS1_5 = 0
CKDIR Bit
M
3
2
0
C
f o
8 /
4
4
BT1
) T
2 x (setting value + 2)
Set to "11
Select divide ratio of count source
Set to "0"
Set to "0001 0010
Set to "0000 0111
Set to "0000 0110
Set to "0000 0010
Set to "0000 0010
Set bit rate
Set to a value smaller than the G1PO0 register
Set to "0100
Set to "1101
Set to "00
Set to "0"
Select length of stop bit
Select either parity enabled or disabled and either odd parity or even parity
Select either the LSB first or MSB first
Select how the receive interrupt is generated
Transmit buffer empty flag
Transmit register empty flag
Receive complete flag
Set to "1" to enable transmission and reception
Set to "1" to enable reception
Set to "1"
Set to "1"
Write data to be transmitted
Received data and error flag are stored
Set to "00
9
5
divided by six or more.
16
PSL1_3 = 0
-
to FFFD
f
2
2
2
CCS2 Bit
BT1
" (f
"
"
2
2
"
"
1
0
)
16
2
2
2
2
2
CCS Register
"
"
"
"
"
Setting
PSC_3 = 1
-
= transfer clock frequency
CCS3 Bit
22. Intelligent I/O (Communication Function)
-
PD7_5 = 0
0
Function
2
" (communication function output
-
IPS1 = 0
Register
G1POCR0
-
(1)