M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 255

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
M
R
R
17.5 Special Mode 3 (GCI Mode)
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E
3
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2
Table17.24 GCI Mode Specifications
0
Clock Synchronization Function Trigger signal input from the CTSi pin
NOTES:
C
In GCI mode, the external clock is synchronized with the transfer clock used in the clock synchronous serial
I/O mode.
Table 17.24 lists specifications of GCI mode. Table 17.25 lists registers settings. Tables 17.26 to 17.28 list
pin settings.
Transfer Data Format
Transfer Clock
1
Transmit/Receive Start
Condition
Interrupt Request
Generation Timing
Error Detection
9
8 /
0 .
B
1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to
0
1
4
0
"1" (interrupt requested).
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3
J
6
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o r
Item
0 -
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u
0
1
p
, 7
0
1
(
2
M
0
3
0
2
5
C
8 /
Page 232
, 4
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To start data transmission and reception, meet the following conditions and then apply a
trigger signal to the CTSi pin:
• While transmitting, the following condition can be selected:
• While receiving,
Overrun error
Transfer data : 8 bits long
The CKDIR bit in the UiMR register (i=0 to 4) is set to "1" (external clock selected):
input from the CLKi pin
- Set the TI bit in the UiC1 register to "0" (Data in the UiTB register)
- Set the TE bit in the UiC1 register to "1" (transmit enable)
- Set the RE bit in the UiC1 register to "1" (receive enable)
- The UiIRS bit in the UiC1 register is set to "0" (UiTB register empty):
- The UiIRS bit is set to "1" (Transmit completed):
This error occurs when the seventh bit of the next received data is read before reading the
UiRB register.
when data is transferred from the UiTB register to the UARTi transmit register (transmission started)
3
when a data transmission from the UARTi transfer register is completed
completed)
when data is transferred from the UARTi receive register to the UiRB register (reception
2
C
8 /
f o
4
4
) T
9
5
(1)
________
________
Specification
17. Serial I/O (Special Function)