M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 391

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
M
R
R
23.4 CAN Interrupts
e
E
3
. v
J
2
Figure 23.40 Operation Timing when CAN Bus Error Occurs
0
C
23.3.4 CAN Bus Error Timing
The CAN0 wake-up interrupt and CAN0j interrupts (j=0 to 2) are provided as the CAN interrupt.
23.4.1 CAN0 Wake-Up Interrupt
23.4.2 CAN0j Interrupts
1
9
0 .
8 /
B
Figure 23.40 shows an operation example of when a CAN bus error occurs.
If P7
counter mode of the timer A3 (TA3
If P8
that shares a pin with CAN0
Figure 23.41 shows a block diagram of the CAN0j interrupts. The followings cause the CAN-associated
interrupt request to be generated.
The INTSEL bit in the C0CTLR1 register determines how an interrupt request is generated. When the
INTSEL bit is set to "0", one of the above CAN0 interrupt request source causes the CAN0j interrupts to
be generated by the OR circuit. When the INTSEL bit is set to "1", CAN0 transmission completed, CAN0
reception completed and CAN0 errors (CAN0 bus error detection, CAN0 module into error-passive state
and CAN0 module into bus-off state) cause the CAN0j interrupt corresponding to each source to be
generated.
- The CAN0 slot k (k=0 to 15) completes a transmission
- The CAN0 slot k completes a reception
- The CAN0 module detects a bus error
- The CAN0 module moves into an error-passive state
- The CAN0 module moves into a bus-off state
0
1
4
0
(1) When a CAN bus error is detected, the STATE_BUSERROR bit in the C0STR register is set to
3
G
J
6
u
3
7
o r
0 -
. l
(CAN0
"1", (error occurred) and the BEIS bit in the C0EISTR register is set to "1" (interrupt requested).
The CAN starts transmitting the error frame.
(CAN0
u
0
1
p
, 7
0
1
(
2
M
CAN bus
BEIS bit
STATE_BUSERROR
bit
0
3
0
IN
IN
2
5
) is used as a CAN input port, the CAN0 wake-up interrupts are available by using INT1
) is used as a CAN0 input port, the CAN0 wake-up interrupt is available by using event
C
8 /
Page 368
, 4
M
3
2
C
f o
8 /
IN
4
4
.
) T
9
5
"1"
"1"
"0"
"0"
IN
Transmit / receive frame
) that shares a pin with CAN0
(1)
Error detected
Error frame
IN
.
23. CAN Module
________