M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 220

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
M
R
R
e
E
3
. v
J
2
Figure 17.4 U0C0 to U4C0 Registers
0
C
1
9
0 .
8 /
B
0
1
4
0
3
G
J
6
u
o r
0 -
. l
UARTi Transmit/Receive Control Register 0
u
0
1
b7
NOTES:
p
, 7
0
1
(
b6
2
2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
3. The UFORM bit setting is enabled when the SMD2 to SMD0 bits in the UiMR register are set to
1. P7
M
0
Set the UFORM bit to "1" when setting the SMD2 to SMD0 bits to"010
3
setting them to "100
0
b5
"001
5
2
0
C
b4
/TxD2 and P7
2
8 /
" (clock syncronous serial I/O mode) or "101
Page 197
b3
, 4
M
b2
3
2
b1
C
1
f o
b0
8 /
/SCL2 are ports for the N-channel open drain output, but not for the CMOS output.
2
4
4
" (UART mode, 7-bit transfer data) or "110
) T
UFORM
9
TXEPT
Symbol
CKPOL
CLK0
CLK1
5
CRS
CRD
NCH
Bit
Symbol
U0C0 to U4C0
Data Output Select
Bit
UiBRG Count
Source Select Bit
CST/RTS Function
Select Bit
Transmit Register
Empty Flag
CTS/RTS Disable
Bit
CLK Polarity
Select Bit
Transfer Format
Select Bit
(1)
Bit Name
(3)
Address
036C
16,
2
" (UART mode, 8-bit transfer data).
02EC
b1
0 0: Selects f
0 1: Selects f
1 0: Selects f
1 1: Do not set to this value
Enabled when CRD=0
0 : Selects CTS function
1 : Selects RTS function
0 : Data in the transmit register
1 : No data in the transmit register
0 : Enables CTS/RTS function
1 : Disables CTS/RTS function
0 : TxDi/SDAi and SCLi are ports for the
1 : TxDi/SDAi and SCLi are ports for the
0 : Data is transmitted on the falling edge
1 : Data is transmitted on the rising edge of
0 : LSB first
1 : MSB first
b0
(during transmission)
(transmission is completed)
CMOS output
N-channel open drain output
of the transfer clock and data is
received on the rising edge
the transfer clock and data is received
on the falling edge
16,
033C
(i=0 to 4)
2
16,
" (UART mode, 9-bit transfer data).
1
8
2n (2)
032C
2
" (I
Function
16,
2
02FC
C mode), or to "0" when
16
After Reset
0000 1000
2
RW
RW
RW
RW
RW
RW
RW
RW
RO
17. Serial I/O