M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 133
Manufacturer Part Number
IC M32C MCU FLASH 512K 144LQFP
Renesas Electronics America
Specifications of M30845FJGP#U3
CAN, I²C, IEBus, SIO, UART/USART
DMA, PWM, WDT
Number Of I /o
Program Memory Size
512KB (512K x 8)
Program Memory Type
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
A/D 34x10b, D/A 2x8b
-40°C ~ 85°C
Package / Case
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
11.4 High-Speed Interrupt
11.5 Interrupts and Interrupt Vectors
Figure 11.2 Interrupt Vector
The high-speed interrupt executes an interrupt sequence in five cycles and returns from the interrupt in
When the FSIT bit in the RLVL register is set to "1" (interrupt priority level 7 available for the high-speed
interrupt), the ILVL2 to ILVL0 bits in the interrupt control registers can be set to "111
Only one interrupt can be set as the high-speed interrupt. When using the high-speed interrupt, do not set
multiple interrupts to interrupt priority level 7. Set the DMAII bit in the RLVL register to "0" (interrupt priority
level 7 available for interrupts).
Set the starting address of the high-speed interrupt routine in the VCT register.
When the high-speed interrupt is acknowledged, the FLG register is saved into the SVF register and PC is
saved into the SVP register. The program is executed from an address indicated by the VCT register.
Execute the FREIT instruction to return from the high-speed interrupt routine.
The values saved into the SVF and SVP registers are restored to the FLG register and PC by executing the
The high-speed interrupt and the DMA2 and DMA3 use the same register. When using the high-speed
interrupt, neither DMA2 nor DMA3 is available. DMA0 and DMA1 can be used.
There are four bytes in one vector. Set the starting address of interrupt routine in each vector table. When
an interrupt request is acknowledged, the interrupt routine is executed from the address set in the interrupt
Figure 11.2 shows the interrupt vector.
Vector Address + 0
Vector Address + 1
Vector Address + 2
Vector Address + 3
Middle-order bits of an address
High-order bits of an address
Low-order bits of an address
" (level 7) to use the