M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 133

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
R
R
M
11.4 High-Speed Interrupt
11.5 Interrupts and Interrupt Vectors
e
E
3
. v
J
2
Figure 11.2 Interrupt Vector
0
C
The high-speed interrupt executes an interrupt sequence in five cycles and returns from the interrupt in
three cycles.
When the FSIT bit in the RLVL register is set to "1" (interrupt priority level 7 available for the high-speed
interrupt), the ILVL2 to ILVL0 bits in the interrupt control registers can be set to "111
high-speed interrupt.
Only one interrupt can be set as the high-speed interrupt. When using the high-speed interrupt, do not set
multiple interrupts to interrupt priority level 7. Set the DMAII bit in the RLVL register to "0" (interrupt priority
level 7 available for interrupts).
Set the starting address of the high-speed interrupt routine in the VCT register.
When the high-speed interrupt is acknowledged, the FLG register is saved into the SVF register and PC is
saved into the SVP register. The program is executed from an address indicated by the VCT register.
Execute the FREIT instruction to return from the high-speed interrupt routine.
The values saved into the SVF and SVP registers are restored to the FLG register and PC by executing the
FREIT instruction.
The high-speed interrupt and the DMA2 and DMA3 use the same register. When using the high-speed
interrupt, neither DMA2 nor DMA3 is available. DMA0 and DMA1 can be used.
There are four bytes in one vector. Set the starting address of interrupt routine in each vector table. When
an interrupt request is acknowledged, the interrupt routine is executed from the address set in the interrupt
vectors.
Figure 11.2 shows the interrupt vector.
1
9
0 .
8 /
B
0
1
4
0
3
G
J
6
u
o r
0 -
. l
u
0
1
, 7
0
p
1
(
2
M
0
0
3
5
2
Vector Address + 0
Vector Address + 1
Vector Address + 2
Vector Address + 3
C
8 /
Page 110
, 4
M
3
2
C
f o
8 /
4
4
) T
9
5
MSB
Middle-order bits of an address
High-order bits of an address
Low-order bits of an address
0 0
16
LSB
2
" (level 7) to use the
11. Interrupts