M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 226

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
R
R
M
17.1 Clock Synchronous Serial I/O Mode
e
E
3
. v
J
2
Table 17.1 Clock Synchronous Serial I/O Mode Specifications
NOTES:
0
Transfer Data Format
Transfer Clock
Transmit/Receive Control
Transmit Start Condition
Receive Start Condition
Interrupt Request Generation Timing • While transmitting, the following conditions can be selected:
Error Detect
Selectable Function
C
In clock synchronous serial I/O mode, data is transmitted and received with the transfer clock. Table 17.1
lists specifications of clock synchronous serial I/O mode. Table 17.2 lists register settings. Tables 17.3 to
17.5 list pin settings. When UARTi (i=0 to 4) operating mode is selected, the TxDi pin outputs a high-level
("H") signal before transfer starts (the TxDi pin is in a high-impedance state when the N-channel open drain
output is selected). Figure 17.10 shows transmit and receive timings in clock synchronous serial I/O mode.
1
9
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
2. To start transmission/reception when selecting the external clock, these conditions must be met after the CKPOL
3. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to "1"
0 .
8 /
B
0
1
4
bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and data is received
on the rising edge) and the CLKi pin is held "H", or when the CKPOL bit is set to "1" (data is transmitted on the rising
edge of the transfer clock and data is received on the falling edge) and the CLKi pin is held "L".
(interrupt requested).
0
3
G
J
6
u
Item
o r
0 -
. l
u
0
1
, 7
0
p
1
(
2
M
0
0
3
5
2
C
8 /
Page 203
, 4
M
3
2
• The CKDIR bit in the UiMR register (i=0 to 4) is set to "0" (internal clock selected):
• The CKDIR bit is set to "1" (external clock selected) : an input from the CLKi pin
Selected from the CTS function, RTS function or CTS/RTS function disabled
To start transmitting, the following requirements must be met
• While receiving
Overrun error
• CLK polarity
• LSB first or MSB first
• Continuous receive mode
• Serial data logic inverse
Transfer data : 8 bits long
To start receiving, the following requirements must be met
C
This error occurs when the seventh bit of the next received data is read before reading
- Set the TE bit in the UiC1 register to "1" (transmit enable)
- Set the TI bit in the UiC1 register to "0" (data in the UiTB register)
- Apply a low-level ("L") signal to the CTSi pin when the CTS function is selected
- Set the RE bit in the UiC1 register to "1" (receive enable)
- Set the TE bit to "1" (transmit enable)
- Set the TI bit to "0" (data in the UiTB register)
- The UiIRS bit in the UiC1 register is set to "0" (no data in the transmit buffer):
- The UiIRS bit is set to "1" (transmission completed):
the UiRB register
When data is transferred from the UARTi receive register to the UiRB register (reception completed)
f o
8 /
when data is transferred from the UiTB register to the UARTi transmit register (transfer started)
2(m+1)
when a data transfer from the UARTi transmit register is completed
Data is transmitted or received in either bit 0 or in bit 7
Data can be received simultaneously by reading the UiRB register
This function inverses transmitted/received data logically
Transferred data output and input are provided on either the rising edge or falling edge
of the transfer clock
4
4
f
) T
9
j
5
(3)
f
j
=f
1
, f
_______
8
, f
2
n
(1)
m
:setting value of the UiBRG register, 00
_______
Specification
________
17. Serial I/O (Clock Synchronous Serial I/O)
_______ _______
_______
(2)
:
(2)
:
16
to FF
16