M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 248
Manufacturer Part Number
IC M32C MCU FLASH 512K 144LQFP
Renesas Electronics America
Specifications of M30845FJGP#U3
CAN, I²C, IEBus, SIO, UART/USART
DMA, PWM, WDT
Number Of I /o
Program Memory Size
512KB (512K x 8)
Program Memory Type
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
A/D 34x10b, D/A 2x8b
-40°C ~ 85°C
Package / Case
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
17.3.6 SDA Input
17.3.7 ACK, NACK
17.3.8 Transmit and Receive Reset
When the IICM2 bit in the UiSMR2 register (i=0 to 4) is set to "0", the first eight bits of received data are
stored into bits 7 to 0 (D
When the IICM2 bit is set to "1", the first seven bits (D
in the UiRB register. Store the eighth bit (D
If the IICM2 bit is set to "1" and the CKPH bit in the UiSMR3 register is set to "1", the same data as that of
when setting the IICM2 bit to "0" can be read. To read the data, read the UiRB register after the rising
edge of the ninth bit of the transfer clock.
When the STSPSEL bit in the UiSMR4 register (i=0 to 4) is set to "0" (serial I/O circuit selected) and the
ACKC bit in the UiSMR4 register is set to "1" (ACK data output), the SDAi pin provides the value output
set in the ACKD bit in the UiSMR4 register.
If the IICM2 bit is set to "0", the NACK interrupt request is generated when the SDAi pin is held high ("H")
on the rising edge of the ninth bit of the transfer clock. The ACK interrupt request is generated when the
SDAi pin is held low ("L") on the rising edge of the ninth bit of the transfer clock.
When ACK is selected to generate a DMA request, the DMA transfer is activated by an ACK detection.
When the STC bit in the UiSMR2 register (i=0 to 4) is set to "1" (UARTi initialization enabled) and a start
condition is detected,
If UARTi transmission and reception are started with this function, the TI bit in the UiC1 register remains
unchanged. Select the external clock as the transfer clock when using this function.
- the transmit shift register is reset and the content of the UiTB register is transferred to the transmit shift
- the receive shift register is reset and the first bit start receiving when the next clock is applied.
- the SWC bit is set to "1" (SCL wait output enabled). The SCLi pin becomes "L" on the falling edge of the
register. The first bit starts transmitting when the next clock is input. UARTi output value remains
unchanged between when the clock is applied and when the first bit data output is provided. The value
remains the same as when start condition was detected.
ninth bit of the transfer clock.
) in the UiRB register. The ninth bit (D
) into bit 8 in the UiRB register.
) of received data are stored into bits 6 to 0
) is ACK or NACK.
17. Serial I/O (Special Function)