M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 221

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
M
R
R
e
E
3
. v
J
2
Figure 17.5 U0C1 to U4C1 Registers and U0SMR to U4SMR Registers
0
C
1
9
0 .
8 /
B
0
1
4
0
3
G
J
6
u
o r
0 -
. l
u
0
1
p
, 7
0
UARTi Special Mode Register
b7
1
NOTES:
(
UARTi Transmit/Receive Control Register 1
b7
2
M
NOTES:
b6
0
1. The BBS bit is set to "0" by program. It is unchanged if set to "1".
2. UART0: timer A3 underflow signal, UART1: timer A4 underflow signal,
3. Refer to notes for the SU1HIM bit in the UiSMR2 register.
3
0
b6
1. Set the SCLKSTPB/UiERE bit after setting the SMD2 to SMD0 bits in the UiMR register.
2. The UiLCH bit setting is enabled when setting the SMD2 to SMD0 bits to "001
UART2: timer A0 underflow signal, UART3: timer A3 underflow signal,
UART4: timer A4 underflow signal.
2
5
b5
C
Set the UiLCH bit to "0" when setting the SMD2 to SMD0 bits to"010
mode, 9-bit transfer data).
b5
serial I/O mode), "100
b4
8 /
Page 198
b4
, 4
b3
b3
M
b2
3
b2
2
b1
C
b1
b0
f o
8 /
b0
4
4
SCLKDIV
ABSCS
Symbol
) T
LSYN
ACSE
9
SCLKSTPB
/UiERE
IICM
ABC
BBS
SSS
UiRRM
2
UiIRS
UiLCH
Bit
5
Symbol
" (UART mode, 7-bit transfer data) or "101
Symbol
U0SMR to U4SMR
RE
TE
TI
RI
Bit
Symbol
U0C1 to U4C1
Bus Conflict Detect
Sampling Clock Select Bit
Auto Clear Function Select
Bit for Transmit Enable Bit
Arbitration Lost Detect
Flag Control Bit
SCLL Sync Output
Enable Bit
I
Bus Busy Flag
Transmit Start
Condition Select Bit
Clock Divide
Synchronous Bit
2
Transmit
Enable Bit
Transmit Buffer
Empty Flag
Receive
Enable Bit
Receive
Complete Flag
UARTi Transmit
Interrupt Cause
Select Bit
UARTi
Continuous
Receive Mode
Enable Bit
Data Logic
Select Bit
Clock-Divided
Synchronous Stop
Bit /
Error Signal
Output Enable
Bit
C Mode Select Bit
(1)
Bit Name
Bit Name
(i=0 to 4)
(2)
Address
036D
Address
0367
0: Transmit disable
1: Transmit enable
0: Data in the UiTB register
1: No data in the UiTB register
0: Receive disable
1: Receive enable
0: No data in the UiRB register
1: Data in the UiRB register
0: No data in the UiTB register (TI = 1)
1: Transmission is completed (TXEPT = 1)
0: Disables continuous receive mode to be entered
1: Enables continuous receive mode to be entered
0: Not inversed
1: Inverse
Clock-divided synchronous stop bit (special mode 3)
0: Stops synchronizing
1: Starts synchronizing
Error signal output enable bit (special mode 5)
0: Not output
1: Output
16,
16,
02ED
02E7
0: Except I
1: I
0: Update per bit
1: Update per byte
0: Stop condition detected
1: Start condition detected (Busy)
0: Disabled
1: Enabled
0: Rising edge of transfer clock
1: Timer Aj underflow
0: Not related to RxDi
1: Synchronized with RxDi
(Note 3)
0: No auto clear function
1: Auto clear at bus conflict
16,
16,
2
C mode
033D
0337
(i=0 to 4)
16,
16,
2
2
C mode
032D
" (UART mode, 8-bit transfer data).
0327
Function
2
Function
" (I
16,
16,
2
C mode) or "110
02FD
02F7
(j=0 to 4)
2
16
16
" (clock syncronous
After Reset
(2)
00
After Reset
0000 0010
16
2
" (UART
RW
RW
RW
RW
RW
RW
RW
RW
RW
2
RW
RW
RW
RW
RW
RW
RW
RO
RO
(1)
17. Serial I/O