M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 236

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
R
R
M
e
E
3
. v
J
2
Figure 17.15 Receive Operation
Table 17.11 Transfer Speed
0
C
1
17.2.1 Transfer Speed
9
B
0 .
8 /
B
t i
b (
In UART mode, transfer speed is clock frequency which is divided by a setting value of the UiBRG (i=0 to
4) register and again divided by 16. Table 17.11 lists an example of transfer speed setting.
1
1
2
3
3
5
0
1
4
R
p
1
2
4
9
4
9
8
1
8
1
0
) s
a
2
4
8
6
4
2
8
2
4
2
3
G
8-bit Data Reception Timing (with no parity and 1 stop bit)
J
Output from
UiBRG
RxDi
Transfer Clock
RI bit in UiC1
register
RTSi
IR bit in SiRIC
register
e t
RE bit in UiC1
register
0
0
0
0
0
0
0
5
0
0
6
u
o r
0
0
0
0
0
0
0
0
0
0
0 -
. l
u
0
1
, 7
0
p
S
U
C
1
o
(
B i
2
o
M
f o
8 f
8 f
8 f
u
1 f
1 f
1 f
1 f
1 f
1 f
1 f
0
u
R
c r
t n
0
3
G
e
5
2
C
i=0 to 4
NOTES:
8 /
Page 213
"1"
"0"
"1"
"0"
"H"
"L"
"1"
"0"
S
1. The above applies when the PRYE bit in the UiMR register is set to "0" (parity disabled),
f o
, 4
t e
P
Start receiving when the transfer clock is
generated on the falling edge of the start bit
the STPS bit in the UiMR register is set to "0" (1 stop bit) and the CRS bit in the UiC0 register is set
to "1" (RTS function selected).
U
n i t
r e
M
1
1
B i
3
0
5
2
0
6
5
3
2
1
g
p i
3
1
R
3
1
5
3
8
1
4
5
9
V
h
2
: G
1 (
6 (
3 (
1 (
6 (
4 (
3 (
2 (
1 (
1 (
r e
a
C
u l
F
l a
7
3
9
7
4
3
2
9
3
f o
8 /
n
e
1
) h
) h
) h
) h
) h
) h
) h
) h
) h
) h
4
F
6
4
M
u
) T
9
Start bit
n
5
H
A
t c
z
c
o i
u t
Verify if an "L"
signal is applied
n
l a
b (
C
B
p
o l
t i
) s
3
3
5
1
1
2
c
R
1
2
4
9
4
1
8
0
9
8
: k
2
4
8
6
4
2
4
0
a
Set to "0" by an interrupt request acknowledgement or by program
2
5
0
e t
0
0
1
9
5
6
0
3
7
2
4
8
5
3
0
2
0
1
1
S
D
f o
t e
0
P
U
n i t
r e
1
1
1
Capture a received data
B i
2
5
7
3
5
0
7
5
4
3
Data is transferred from the UARTi receive
register to the UiRB register
p i
g
8
R
7
5
7
8
5
3
7
1
8
h
V
: G
1 (
Change to "L" by reading the UiRB register
2 (
9 (
4 (
2 (
9 (
6 (
4 (
3 (
2 (
r e
a
u l
C
6
6
6
6
7
6
3
F
6
l a
n
2
e
) h
) h
) h
) h
) h
) h
) h
) h
) h
) h
F
4
M
u
D
n
H
A
1
t c
z
c
o i
u t
n
l a
b (
D
C
B
p
7
o l
) s
t i
1
2
3
3
5
1
c
R
1
2
4
9
8
1
8
1
4
9
: k
a
2
4
8
6
4
8
2
4
7
2
e t
0
0
0
1
4
5
6
2
2
3
2
4
8
5
3
6
0
2
4
1
Stop bit
S
f o
P
t e
r e
U
n i t
2
2
1
1
1
B i
p i
0
0
3
6
0
5
0
6
5
3
g
7
7
R
8
3
1
3
8
3
1
8
h
V
r e
: G
(
(
8 (
6 (
3 (
6 (
4 (
3 (
3 (
2 (
17. Serial I/O (UART)
a
C
C
l a
u l
A
F
F
F
7
3
7
4
3
6
n
3
e
) h
) h
) h
) h
) h
) h
) h
) h
) h
) h
2
F
M
u
n
H
A
t c
z
c
o i
u t
n
l a
b (
C
B
p
o l
) s
1
2
3
3
5
t i
1
2
c
1
4
9
4
8
1
8
1
9
R
: k
2
4
8
6
3
9
2
4
2
2
a
0
8
0
0
1
8
5
6
8
3
e t
2
4
8
5
8
6
0
2
2
1