M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 199

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
R
R
M
e
E
3
. v
J
2
Table 15.9 Timer Mode Specifications
NOTES:
Figure 15.20 TB0MR to TB5MR Registers
0
Count Source
Counting Operation
Divide Ratio
Counter Start Condition
Counter Stop Condition
Interrupt Request Generation Timing Timer counter underflows
TBi
Read from Timer
Write to Timer
C
15.2.1 Timer Mode
1
9
0 .
8 /
B
In timer mode, the timer counts an internally generated count source (see Table 15.9). Figure 15.20
shows the TBiMR register (i=0 to 5) in timer mode.
IN
0
1
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
4
0
Pin Function
3
G
J
6
u
Item
o r
0 -
. l
Timer Bi Mode Register
b7
u
NOTES:
0
1
p
, 7
0
b6
1
1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
(
2
M
0
b5
0
3
0
5
2
b4
C
8 /
Page 176
b3
, 4
b2
M
3
b1
0 0
2
f
• The timer decrements a counter value
1/(n+1)
The TBiS bits in the TABSR and TBSR registers are set to "1" (starts counting)
The TBiS bit is set to "0" (stops counting)
Programmable I/O port
The TBi register indicates counter value
• When the timer counter stops, the value written to the TBi register is also written to
• While counting, the value written to the TBi register is written to the reload register
1
When the timer counter underflows, content of the reload register is reloaded into the
both reload register and counter
(It is transferred to the counter at the next reload timing)
C
, f
count register and counting resumes
b0
f o
8 /
8
, f
4
4
TMOD0
TMOD1
Symbol
2n (1)
) T
TCK0
TCK1
9
MR0
MR2
MR3
MR1
Bit
5
Symbol
TB0MR to TB5MR 035B
, f
n
: setting value of the TBi register (i=0 to 5)
C32
(i=0 to 5)
Operating Mode
Select Bit
Disabled in timer mode.
Can be set to "0" or "1".
TB0MR, TB3MR registers:
TB1MR, TB2MR TB4MR, TB5MR registers:
Set to "0" in timer mode
Count Source
Select Bit
Set to "0" in timer mode
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Bit Name
(Timer Mode)
Address
16
, 035C
Specification
16
, 035D
b7 b6
b1b0
0 0 : f
0 1 : f
1 0 : f
1 1 : f
0 0 : Timer mode
16
1
8
2n (1)
C32
, 031B
16
Function
, 031C
16
, 031D
0000
16
16
After reset
00XX 0000
to FFFF
15. Timer (Timer B)
RW
RW
RW
RW
RW
RW
RW
RW
RW
16
2