M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 375

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
R
R
e
E
3
. v
J
2
Figure 23.26 C0GMR4, C0LMAR4 and C0LMBR4 Registers
0
C
1
9
0 .
8 /
B
0
1
4
0
3
G
J
6
u
o r
0 -
. l
CAN0 Global Mask Register Extended ID2
CAN0 Local Mask Register A Extended ID2
CAN0 Local Mask Register B Extended ID2
b7
u
0
1
NOTES:
p
, 7
0
b6
1
(
1. The C0GMR4, C0LMAR4 and C0LMBR4 registers can be accessed only when the BANKSEL bit in
3. The C0LMAR4 register shares the same address with the C0MCTL4 register.
4. The C0LMBR4 register shares the same address with the C0MCTL12 register.
2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) after
2
M
0
b5
the C0CTLR1 register is set to "1" (mask register selected).
reset, supplying the clock to the CAN module, and setting the BANKSEL bit to "0".
3
0
2
5
b4
C
8 /
Page 352
b3
, 4
b2
M
3
b1
2
C
b0
f o
8 /
4
4
Symbol
(b7 - b6)
) T
EID0M
EID1M
EID2M
EID3M
EID4M
EID5M
9
Bit
5
Symbol
C0GMR4
C0LMAR4
C0LMBR4
Extended ID0
Extended ID1
Extended ID2
Extended ID3
Extended ID4
Extended ID5
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Bit Name
Address
022C
0234
023C
16
16
16
0: No ID is verified
1: ID is verified
(1)
(3)
(1)
(4)
(1)
Function
After Reset
XX00 0000
XX00 0000
XX00 0000
2
2
2
(2)
23. CAN Module
RW
RW
RW
RW
RW
RW
RW

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