M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 495
Manufacturer Part Number
IC M32C MCU FLASH 512K 144LQFP
Renesas Electronics America
Specifications of M30845FJGP#U3
CAN, I²C, IEBus, SIO, UART/USART
DMA, PWM, WDT
Number Of I /o
Program Memory Size
512KB (512K x 8)
Program Memory Type
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
A/D 34x10b, D/A 2x8b
-40°C ~ 85°C
Package / Case
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
27.5 Clock Generation Circuit
27.5.1 CPU Clock
27.5.2 Sub Clock
• When the CPU operating frequency is 24 MHz or more, use the following procedure for better EMC
• In M32C/84T, the main clock frequency must be 24 MHz or less.
Set the CM03 bit to "0" (X
the CPU clock, or timer A or timer B count source (f
(Electromagnetic Compatibility) performance.
18.104.22.168 Sub Clock Oscillation
22.214.171.124 Using Stop Mode
126.96.36.199 Oscillation Parameter Matching
When oscillating the sub clock, set the CM04 bit in the CM0 register to "1" (X
function) after setting the CM07 bit in the CM0 register to "0" (clock other than sub clock) and the
CM03 bit to "1" (X
Set the sub clock as the CPU clock, or timer A or timer B count source (f
When the microcomputer enters stop mode, the CM03 bit is automatically set to "1" (X
capacity "HIGH"). Use the following procedure to select the main clock as the CPU clock when enter-
ing stop mode.
After exiting stop mode, wait for the sub clock oscillation to stabilize. Then set the CM03 bit to "0" and
the CM07 bit to "1" (sub clock).
If the sub slock oscillation parameters have only been evaluated with the drive capacity "HIGH", the
parameters should be reevaluated for drive capacity "LOW".
Contact your oscillator manufacturer for details on matching parameters.
1) Oscillator connected between the X
2) Use the PLL frequency synthesizer to multiply the main clock.
1) Set the CM17 bit in the CM1 register to "0" (main clock).
2) Set the CM21 bit in the CM2 register to "0" (clock selected by the CM17 bit).
3) Set the CM07 bit in the CM0 register to "0" (clock selected by the CM21 bit divided by the MCD
pin, has less than 24 MHz frequency.
drive capacity "HIGH"). Set the CM03 bit to "0" after sub clock oscillation
drive capacity "LOW") when selecting the sub clock (X
pins, or external clock applied to the
27. Precautions (Clock Generation Circuit)
) after the above settings