M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 231

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
R
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3
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2
Figure 17.13 Serial Data Logic Inverse
0
C
17.1.3 Continuous Receive Mode
17.1.4 Serial Data Logic Inverse
1
9
8 /
0 .
B
When the UiRRM bit in the UiC1 register (i=0 to 4) is set to "1" (continuous receive mode), the TI bit is set
to "0" (data in the UiTB register) by reading the UiRB register. When the UiRRM bit is set to "1", do not set
dummy data in the UiTB register by program.
When the UiLCH bit (i=0 to 4) in the UiC1 register is set to "1" (inverse), data logic written in the UiTB
register is inversed when transmitted. The inversed receive data logic can be read by reading the UiRB
register. Figure 17.13 shows a switching example of the serial data logic.
0
1
4
0
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3
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6
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u
0
1
p
, 7
0
1
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2
M
0
3
0
2
5
(2) When the UiLCH bit in the UiC1 register is set to "1" (inverse)
Transfer clock
(1) When the UiLCH bit in the UiC1 register (i=0 to 4) is set to "0" (not inversed)
Transfer clock
NOTES:
C
8 /
1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on
(no inverse)
Page 208
the falling edge) and the UFORM bit in the UiC register is set to "0" (LSB first).
, 4
(inverse)
M
TxD
TxD
3
2
i
i
C
"H"
"H"
"H"
"H"
"L"
8 /
"L"
"L"
"L"
f o
4
4
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9
5
D
D
0
0
D
D
1
1
D
D
2
2
D
D
3
3
D
D
4
4
17. Serial I/O (Clock Synchronous Serial I/O)
D
D
5
5
D
D
6
6
D
D
7
7

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