M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 158

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
M
R
R
13. DMAC
e
E
3
. v
J
2
Figure 13.1 Register Mapping for DMAC
0
C
This microcomputer contains four DMAC (direct memory access controller) channels that allow data to be
sent to memory without using the CPU. DMAC transmits a 8- or 16-bit data from a source address to a
destination address whenever a transmit request occurs. DMA0 and DMA1 must be prioritized if using
DMAC. DMA2 and DMA3 share registers required for high-speed interrupts. High-speed interrupts cannot
be used when using three or more DMAC channels.
The CPU and DMAC use the same data bus, but DMAC has a higher bus access privilege than the CPU.
The cycle-steal method employed on DMAC enables high-speed operation between a transfer request and
the complete transmission of 16-bit (word) or 8-bit (byte) data. Figure 13.1 shows a mapping of registers to
be used for DMAC. Table 13.1 lists specifications of DMAC. Figures 13.2 to 13.5 show registers associ-
ated with DMAC.
Because the registers shown in Figure 13.1 are allocated in the CPU, use the LDC instruction to write to the
registers. To set the DCT2, DCT3, DRC2, DRC3, DMA2 and DMA3 registers, set the B flag to "1" (register
bank 1) and set the R0 to R3, A0 and A1 registers with the MOV instruction.
To set the DSA2 and DSA3 registers, set the B flag to "1" and set the SB and FB registers with the LDC
instruction. To set the DRA2 and DRA3 registers, set the SVP and VCT registers with the LDC instruction.
1
9
8 /
0 .
B
When Three or More DMAC Channels are Used,
the Register Bank 1 is Used as DMAC Registers
0
DMAC-Associated Registers
1
4
NOTES:
0
G
3
J
1. Registers are used for repeat transfer, not for single transfer.
6
u
o r
0 -
. l
u
DMA2 (A0)
DMA3 (A1)
DSA3 (FB)
0
1
DSA2 (SB)
p
, 7
0
1
DSA0
DSA1
DRA0
DRA1
DMA0
DMA1
(
DRC2 (R2)
DRC3 (R3)
DCT2 (R0)
DCT3 (R1)
2
M
0
DCT0
3
DCT1
DRC0
DRC1
0
2
5
C
DMD0
DMD1
8 /
Page 135
, 4
DMA2 Transfer Count Register
DMA2 Transfer Count Reload Register
DMA3 Memory Address Register
DMA3 SFR Address Register
DMA3 Transfer Count Register
DMA3 Transfer Count Reload Register
DMA2 Memory Address Register
DMA2 SFR Address Register
M
DMA 0 Transfer Count Register
DMA 1 Transfer Count Reload Register
DMA Mode Register 0
DMA Mode Register 1
DMA 1 Transfer Count Register
DMA 0 Transfer Count Reload Register
DMA 0 Memory Address Register
DMA 1 Memory Address Register
DMA 1 SFR Address Register
DMA 0 Memory Address Reload Register
DMA 1 Memory Address Reload Register
DMA 0 SFR Address Register
3
2
C
8 /
f o
4
4
) T
9
5
(1)
(1)
(1)
(1)
(1)
(1)
When Three or More DMAC Channels are Used,
the High-Speed Interrupt Register is Used as DMAC
Registers
When using DMA2 and DMA3, use the CPU registers shown in parentheses ().
DRA2 (SVP)
DRA1 (VCT)
SVF
DMA2 Memory Address Reload Register
DMA3 Memory Address Reload Register
Flag Save Register
(1)
(1)
13. DMAC