M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 124

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
M
R
R
e
E
3
. v
J
2
0
C
1
9
8 /
0 .
B
0
1
4
9.5.3.1 Entering Stop Mode
0
G
Stop mode is entered when setting the CM10 bit in the CM10 register to "1" (all clocks stops). The
MCD4 to MCD0 bits in the MCD register become set to "01000
Enter stop mode after setting the followings.
3
J
6
• Initial Setting
• Before Entering stop mode
• After Exiting Stop Mode
u
o r
0 -
. l
Set each interrupt priority level after setting the exit priority level, required to exit stop mode, con-
trolled by the RLVL2 to RLVL0 bits in the RLVL register, to "7".
(1) Set the I flag to "0"
(2) Set the interrupt priority level of the interrupt being used to exit stop mode
(3) Set the interrupt priority levels of the interrupts, not being used to exit stop mode, to "0"
(4) Set IPL in the FLG register. Then set the exit priority level to the same level as IPL
(5) Set the PRC0 bit in the PRCR register to "1" (write enable)
(6) Select the main clock as the CPU clock
(7) The oscillation stop detect function is used, set the CM20 bit in the CM2 register to "0" (oscilla-
(8) Set the I flag to "1"
(9) Set the CM10 bit to "1" (all clocks stops)
Set the exit priority level to "7" as soon as exiting stop mode.
u
0
1
p
, 7
0
1
• When the CPU clock source is the sub clock,
• When the CPU clock source is the PLL clock,
• When main clock direct mode is used,
• When the CPU clock source is the on-chip oscillator clock,
tion stop detect fucntion disabled)
(
2
M
(b) set the CM07 bit in the CM0 register to "0" (clock selected by the CM21 bit divided by MCD
(a) set the CM05 bit in the CM0 register to "0" (main clock oscillates)
(a) set the CM17 bit in the CM1 register to "0" (main clock)
(b) set the PLC07 bit in the PLC0 register to "0" (PLL off)
(a) set the PRC1 bit in the PRCR register to "1" (write enable)
(b) set the PM24 bit in the PM2 register to "0" (clock selected by the CM07 bit)
(a) set MCD4 to MCD0 bits to "01000
(b) set the CM05 bit to "0" (main clock oscillates)
(c) set the CM21 bit in the CM2 register to "0" (clock selected by the CM17 bit)
Interrupt priority level of the interrupt used to exit stop mode > IPL = the exit priority level
0
3
0
2
register setting)
5
C
8 /
Page 101
, 4
M
3
2
C
8 /
f o
4
4
) T
9
5
2
" (divide-by-8 mode)
2
" (divide-by-8 mode).
9. Clock Generation Circuit