M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 290

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
R
R
e
E
3
. v
J
2
Figure 19.2 DACON Register, DA0 and DA1 Registers
Figure 19.3 D/A Converter Equivalent Circuit
0
C
1
9
8 /
0 .
B
0
1
4
0
G
3
J
DA0
AV
V
6
u
o r
REF (4)
0 -
. l
D/A Control Register
D/A Register i (i=0, 1)
b7
b7
SS
u
0
1
D/A register 0
p
, 7
0
b6
1
NOTES:
(
2
M
1. The above applies when the DA0 register is set to "2A
2. This
3. To reduce power consumption when the D/A converter is not used, set the DAiE bit (i=0, 1) to "0"
4. V
0
b5
3
0
(output disabled) and the DAi register to "00
2
5
r
b4
C
REF
MSB
8 /
Page 267
b3
circuitry
DA0E
"1"
, 4
is not related to VCUT bit setting in the AD0CON1 register.
"0"
b2
M
2R
0
3
b1
2
is the same for D/A1.
C
b0
b0
8 /
f o
1
4
R
(b7 - b2)
4
Output value of D/A conversion
) T
Symbol
2R
9
DA0E
DA1E
5
Bit
Symbol
DACON
Symbol
DA0, DA1
R
D/A0 Output Enable Bit
D/A1 Output Enable Bit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
2R
Bit Name
R
Function
Address
039C
Address
0398
2R
16
16
16
" to stop current from flowing into the R-2R resistor.
, 039A
R
2R
16
16
0 : Disables an output
1 : Enables an output
0 : Disables an output
1 : Enables an output
".
R
2R
After Reset
XXXX XX00
After Reset
Indeterminate
Function
R
2R
Setting Range
00
16
2
to FF
R
2R
16
19. D/A Converter
2R
RW
RW
RW
RW
RW
LSB

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