M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 142

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
M
R
R
e
E
3
. v
J
2
Figure 11.6 Interrupt Response Time
0
C
11.6.4 Interrupt Response Time
1
9
0 .
8 /
B
Figure 11.6 shows an interrupt response time. Interrupt response time is the period between an interrupt
generation and the execution of the first instruction in an interrupt routine. Interrupt response time in-
cludes the period between an interrupt request generation and the completed execution of an instruction
((a) on Figure 11.6) and the period required to perform an interrupt sequence ((b) on Figure 11.6).
Time (a) varies depending on an instruction being executed. The DIVX instruction requires the longest
time (a); 42 cycles when an immediate value or register is set as the divisor.
When the divisor is a value in the memory, the following value is added.
X is the number of wait states for a divisor space. Y is the number of wait states for the space that stores
indirect addresses. If X and Y are in an odd address or in 8-bit bus space, the X and Y value must be
doubled.
Table 11.4 lists time (b) shown Figure 11.6.
0
1
4
Interrupt request is generated
0
3
G
J
6
u
o r
0 -
. l
(a) Period between an interrupt request generation and the completed execution of an instruction.
(b) Period required to perform an interrupt sequence.
u
0
1
p
, 7
0
1
(
2
M
0
0
3
• Normal addressing
• Index addressing
• Indirect addressing
• Indirect index addressing
5
2
C
8 /
Page 119
, 4
M
3
2
C
Instruction
f o
8 /
4
4
) T
9
Interrupt response time
5
(a)
Interrupt request is acknowledged
Interrupt sequence
: 2 + X
: 3 + X
: 5 + X + 2Y
: 6 + X + 2Y
(b)
Instruction in
interrupt routine
Time
11. Interrupts