M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 318

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
M
R
R
e
E
3
. v
J
2
0
Table 22.10 Phase-Delayed Waveform Output Mode Specifications
Waveform Output Start Condition
Waveform Output Stop Condition
Interrupt Request
OUTC1j Pin
Selectable Function
NOTES:
C
Output Waveform
22.3.2 Phase-Delayed Waveform Output Mode
1
9
8 /
0 .
B
1. Set the FSCj bit in the G1FS register to "0" (waveform generating function selected).
Output signal level of the OUTC1j pin is inversed every time the value of the base timer matches that of
the G1POj register (j=0 to 7). Table 22.10 lists specifications of phase-delayed waveform output mode.
Figure 22.17 lists an example of phase-delayed waveform output mode operation.
0
1
4
0
G
3
J
6
u
o r
0 -
. l
u
0
1
p
, 7
0
Item
1
(
2
M
0
3
0
2
5
C
8 /
Page 295
, 4
M
3
2
C
(1)
8 /
f o
4
4
) T
• Free-running operation
• The base timer is cleared to "0000
The IFEj bit (j=0 to 7) in the G1FE register is set to "1" (channel j function
enabled)
The IFEj bit is set to "0" (channel j function disabled)
The PO1jR bit in the interrupt request register is set to "1" (interrupt
requested) when the value of the base timer matches that of the G1POj
register. (See Figure 11.14)
Pulse signal output pin
• Default value set function: Set starting waveform output level
• Inversed output function
9
(the RST2 and RST1 bits in the G1BCR1 register are set to "00
Cycle
"H" and "L" widths
G1PO0 register (the RST1 bit is set to "1" and the RST2 bit is set to "0")
Cycle
"H" and "L" widths
Waveform output level is inversed to output a waveform from the OUTC1j pin
5
Setting value of the G1POj (j=0 to 7) register is 0000
n : setting value of the G1PO0 register, 0001
Setting value of the G1POj (j=1 to 7) register is 0000
If G1POj register
:
:
:
:
n+2, the output level is not inversed
65536
2(n+2)
65536 x 2
f
f
n+2
f
BT1
BT1
BT1
f
BT1
Specification
16
" by matching the base timer with the
16
to FFFD
16
16
to FFFF
to FFFF
16
2
")
22. Intelligent I/O
16
16