M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 339

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
R
R
M
e
E
3
. v
J
2
NOTES:
Table 22.24 Pin Settings (Continued)
Figure 22.31 Transmit Operation
Figure 22.32 Receive Operation
9 0
C
Name
P11
P11
. 1
Port
1. Set the MOD2 to MOD0 bits in the corresponding register to "111
8 /
Internal
Transfer clock
ISRxD1 pin
RI bit
SIO1RR bit
B
1 0
0
The above applies to the following conditions:
The above applies to the following conditions:
4
0
2
function used).
3 0
• The STPS bit in the G1MR register is set to "0" (1 stop bit)
• The PRYE bit in the G1MR register is set to "0" (parity disabled)
• The UFORM bit in the G1MR register is set to "0" (LSB first)
• The INV bits in the G1POCR0 to G1POCR7 registers are set to "0" (no inverse)
• The IRS bit in the G1MR register is set to "0" (no data in the G1TB register)
• The STPS bit in the G1MR register is set to "0" (1 stop bit)
• The PRYE bit in the G1MR register is set to "0" (parity disabled)
• The UFORM bit in the G1MR register is set to "0" (LSB first)
• The INV bits in the G1POCR0 to G1POCR7 registers are set to "0" (no inverse)
SIO1TR bit
G
Internal
Transfer clock
ISTxD1 pin
TI bit
TXEPT bit
J
- 6
. l u
o r
ISTxD1 output
ISRxD1 input
1 0
u
0
Function
p
, 7
1 0
(
0 2
M
"H"
"L"
"1"
"0"
"1"
"0"
5 0
3
2
C
"H"
"L"
"1"
"0"
"1"
"0"
"1"
"0"
8 /
Page 316
, 4
PS5 Register PD11 Register IPS Register
PS5_0 = 1
PS5_2 = 0
M
3
2
ST
C
f o
8 /
D
Set data in G1TB register
ST
0
4
4
) T
D
5 9
D
1
0
D
D
2
-
PD11_2 = 0
1
D
Setting
D
3
2
D
D
4
3
D
Tc
D
5
4
D
D
Write "0" by program
if setting to "0"
6
5
D
D
7
6
-
IPS1 = 1
SP
D
7
SP
Write "0" by program
if setting to "0"
22. Intelligent I/O (Communication Function)
Register
G1POCR0
-
TI, TXEPT bit : Bits in the G1CR register
SIO1TR bit
ST
Read the G1RB register
SIO1RR bit : Bit in the IIO2IR register
RI bit
Set data in G1TB register
D
ST
0
D
2
D
1
(1)
0
" (output of the communication
D
: Bit in the G1CR register
D
: Bit in the IIO3IR register
2
1
D
3
D
2
D
D
4
3
D
5
D
4
D
D
6
5
D
7
D
6
SP
D
7
SP