M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 141
Manufacturer Part Number
IC M32C MCU FLASH 512K 144LQFP
Renesas Electronics America
1.M30843FWGPU5.pdf (91 pages)
2.M30843FWGPU5.pdf (531 pages)
Specifications of M30845FJGP#U3
CAN, I²C, IEBus, SIO, UART/USART
DMA, PWM, WDT
Number Of I /o
Program Memory Size
512KB (512K x 8)
Program Memory Type
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
A/D 34x10b, D/A 2x8b
-40°C ~ 85°C
Package / Case
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
11.6.3 Interrupt Sequence
The interrupt sequence is performed between an interrupt request acknowledgment and interrupt routine
When an interrupt request is generated while an instruction is executed, the CPU determines its interrupt
priority level after the instruction is completed. The CPU starts the interrupt sequence from the following
cycle. However, in regards to the SCMPU, SIN, SMOVB, SMOVF, SMOVU, SSTR, SOUT or RMPA
instruction, if an interrupt request is generated while executing the instruction, the microcomputer sus-
pends the instruction to start the interrupt sequence.
The interrupt sequence is performed as follows:
(1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading
(2) The FLG register, prior to an interrupt sequence, is saved to a temporary register
(3) Each bit in the FLG register is set as follows:
(4) A temporary register within the CPU is saved to the stack; or to the SVF register for the high-speed
(5) PC is saved to the stack; or to the SVP register for the high-speed interrupt.
(6) The interrupt priority level of the acknowledged interrupt is set in IPL .
(7) A relocatable vector corresponding to the acknowledged interrupt is stored into PC.
After the interrupt sequence is completed, an instruction is executed from the starting address of the
1. Temporary register cannot be modified by users.
the interrupt information is set to "0" (interrupt requested).
• The I flag is set to "0" (interrupt disabled)
• The D flag is set to "0" (single-step disabled)
• The U flag is set to "0" (ISP selected)
for the high-speed interrupt). Then, the IR bit applicable to
within the CPU.