M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 230

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
R
R
M
e
E
3
. v
J
2
Figure 17.11 Transfer Clock Polarity
Figure 17.12 Transfer Format
0
C
17.1.1 Selecting CLK Polarity Selecting
17.1.2 Selecting LSB First or MSB First
1
9
0 .
8 /
B
As shown in Figure 17.11, the CKPOL bit in the UiC0 register (i=0 to 4) determines the polarity of the
transfer clock.
As shown in Figure 17.12, the UFORM bit in the UiC0 register (i=0 to 4) determines a data transfer format.
0
1
4
0
3
G
J
6
u
o r
0 -
. l
u
0
1
, 7
0
p
1
(1) When the CKPOL bit in the UiC0 register (i=0 to 4) is set to "0"
(2) When the CKPOL bit in the UiC0 register is set to "1"
(
2
M
0
(Data is transmitted on the falling edge of the transfer clock and data is received on the rising edge)
(Data is transmitted on the rising edge of the transfer clock and data is received on the falling edge)
0
3
5
2
R
CLK
T
CLK
T
R
C
X
X
X
X
(1) When the UFORM bit in the UiC0 register (i=0 to 4) is set to "0"
(2) When the UFORM bit in the UiC0 register is set to "1" (MSB first)
NOTES:
NOTES:
NOTES:
D
CLK
T
R
8 /
D
D
D
CLK
T
R
Page 207
NOTES:
X
X
i
i
i
i
i
i
X
1. The CLKi pin is held high ("H") when no data is transferred.
2. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first)
3. The CLKi pin is held low ("L") when no data is transferred.
4. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first)
X
2. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is
, 4
D
D
D
1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is
D
i
(LSB first)
i
i
and the UiLCH bit in the UiC1 register is set to "0" (not inversed).
and the UiLCH bit in the UiC1 register is set to "0" (not inversed).
i
i
i
transmitted on the falling edge of the transfer clock and received on the rising
edge) and the UiLCH bit in the UiC1 register is set to "0" (not inversed).
M
transmitted on the falling edge of the transfer clock and received on the rising
edge) and the UiLCH bit in the UiC1 register is set to "0" (not inversed).
3
2
C
f o
8 /
4
D
D
D
4
D
) T
0
0
9
0
0
D
D
D
D
5
7
7
0
0
D
D
D
D
1
1
1
1
D
D
D
D
6
6
1
1
D
D
D
D
2
D
D
2
2
D
2
D
5
5
2
2
D
D
D
D
3
3
D
D
3
D
3
D
4
4
3
3
D
D
D
D
4
4
4
D
D
4
D
D
3
3
4
4
D
D
D
D
5
5
5
D
D
5
D
D
2
2
5
5
17. Serial I/O (Clock Synchronous Serial I/O)
D
D
D
D
6
6
6
6
D
D
D
D
1
1
6
6
D
D
D
D
D
D
7
7
7
7
D
D
0
0
7
7