M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 161

• Manufacturer Part Number: M30845FJGP#U3
• Description: IC M32C MCU FLASH 512K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30845FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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NOTES:
Table 13.2 DMiSL Register (i = 0 to 3) Function
0
C
1
9
1. If the INT3 pin is used for data bus in memory expansion mode or microprocessor mode, a DMA3 interrupt request
2. The falling edge and both edges of a signal applied to the INTj pin (j=0 to 3) cause a DMA request generation. The
3. Use the UkSMR register and UkSMR2 register (k=0 to 4) to switch between the UARTk receive and the ACK
4. The same setting is used to generate an intelligent I/O interrupt 9 request and a CAN interrupt 0 request.
5. The same setting is used to generate an intelligent I/O interrupt 10 request and a CAN interrupt 1 request.
0 .
8 /
b4 b3 b2 b1 b0
B
Setting Value
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
0
cannot be generated by a signal applied to the INT3 pin.
INT interrupt (the POL bit in the INTjlC register, the LVS bit, the IFSR register) is not affected and vice versa.
interrupt as a DMA request source.
To use the ACK interrupt for a DMA reqest, set the IICM bit in the UkSMR register to "1" and the IICM2 bit in the
UkSMR2 register to "0".
1
4
0
3
G
J
6
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o r
0 -
. l
u
0
1
p
, 7
0
1
(
2
M
0
3
0
5
2
Falling Edge of INT0
Both Edges of INT0
C
Interrupt 0 Request
Interrupt 1 Request
Interrupt 2 Request
Interrupt 3 Request
Interrupt 4 Request
8 /
Page 138
Intelligent I/O
Intelligent I/O
Intelligent I/O
Intelligent I/O
Intelligent I/O
, 4
DMA0
M
3
2
C
f o
8 /
4
4
) T
9
5
UART0 Receive or ACK Interrupt Request
UART1 Receive or ACK Interrupt Request
UART2 Receive or ACK Interrupt Request
UART3 Receive or ACK Interrupt Request
UART4 Receive or ACK Interrupt Request
Falling Edge of INT1
Both Edges of INT1
Interrupt 10 Request
Interrupt 9 Request
Interrupt 8 Request
Interrupt 0 Request
Interrupt 1 Request
CAN Interrupt 2
Intelligent I/O
Intelligent I/O
Intelligent I/O
Intelligent I/O
Intelligent I/O
UART0 Transmit Interrupt Request
UART1 Transmit Interrupt Request
UART2 Transmit Interrupt Request
UART3 Transmit Interrupt Request
UART4 Transmit Interrupt Request
Request
DMA1
A/D0 Interrupt Request
DMA Request Source
Timer A0 Interrupt Request
Timer A1 Interrupt Request
Timer A2 Interrupt Request
Timer A3 Interrupt Request
Timer A4 Interrupt Request
Timer B0 Interrupt Request
Timer B1 Interrupt Request
Timer B2 Interrupt Request
Timer B3 Interrupt Request
Timer B4 Interrupt Request
Timer B5 Interrupt Request
Software trigger
(4)
(5)
Falling Edge of INT2
Both Edges of INT2
Interrupt 2 Request
Interrupt 3 Request
Interrupt 4 Request
Interrupt 8 Request
Intelligent I/O
Intelligent I/O
Intelligent I/O
Intelligent I/O
DMA2
(3)
(3)
(3)
(3)
(3)
Falling Edge of INT3
Both Edges of INT3
Interrupt 10 Request
Interrupt 9 Request
Interrupt 0 Request
Interrupt 1 Request
Interrupt 2 Request
Interrupt 3 Request
CAN Interrupt 2
Intelligent I/O
Intelligent I/O
Intelligent I/O
Intelligent I/O
Intelligent I/O
Intelligent I/O
DMA3
Request
(1,2)
(4)
(5)
(1,2)
13. DMAC