M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 100
Manufacturer Part Number
IC M32C MCU FLASH 512K 144LQFP
Renesas Electronics America
1.M30843FWGPU5.pdf (91 pages)
2.M30843FWGPU5.pdf (531 pages)
Specifications of M30845FJGP#U3
CAN, I²C, IEBus, SIO, UART/USART
DMA, PWM, WDT
Number Of I /o
Program Memory Size
512KB (512K x 8)
Program Memory Type
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
A/D 34x10b, D/A 2x8b
-40°C ~ 85°C
Package / Case
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
8.3 Page Mode Control Function
The page mode control functin allows the microcimputer to be read data in the external memory, associ-
ated with page mode, at high speeds. If the 21 high-order bits of consecutive addresses accessed by the
microcomputer remains the same, access time to each address following the first access is shortened.
The EWCRi (i=0 to 3) registers determine how many wait states are inserted to access the first address.
The PWCR0 and PWCR1 registers determine how many wait states are inserted to access the consecu-
tive addresses following the first address.
Use the following procedure to enable the page mode control.
When using the page mode control, access data in all external space only with the page mode control.
It is not allowed to combine the page mode control access and normal access to data in each external
Set the PM05 and PM04 bits in the PM0 register to "00
control function and multiplexed bus cannot be used at the same time.
Figure 8.13 shows the PWCR0 register. Figure 8.14 shows the PWCR1 register. Figure 8.15 shows an
example of the external bus operation with the page mode control function.
The page mode control function can be used in the ROMless version only.
(1) Set the EWCRi04 to EWCRi00 (i=0 to 3) bits in the EWCRi register
(2) Set the PWCRj02 to PWCRj00 (j=0, 1) bits and the PWCRj06 to PWCRj04 bits in the PWCRj register
(3) Set the PWCRj03 and PWCRj07 bits in the PWCRj register to "1" (page mode control enabled)
" (multiplexed bus not used). The page mode