M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 247

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
M
R
R
e
E
3
. v
J
2
0
C
17.3.3 Arbitration
17.3.4 Transfer Clock
17.3.5 SDA Output
1
9
8 /
0 .
B
The ABC bit in the UiSMR register (i=0 to 4) determines an update timing for the ABT bit in the UiRB
register. On the rising edge of the SCLi pin, the microcomputer determines whether a transmit data
matches data input to the SDAi pin.
When the ABC bit is set to "0" (update per bit), the ABT bit is set to "1" (detected-arbitration is lost) as
soon as a data discrepancy is detected. The ABT bit is set to "0" (not detected-arbitration is won) if not
detected. When the ABC bit is set to "1" (update per byte), the ABT bit is set to "1" on the falling edge of
the ninth bit of the transfer clock if any discrepancy is detected. When the ABT bit is updated per byte, set
the ABT bit to "0" between an ACK detection in the first byte data and the next byte data to be transferred.
When the ALS bit in the UiSMR2 register is set to "1" (SDA output stop enabled), the arbitration lost
occurs. As soon as the ABT bit is set to "1", the SDAi pin is placed in a high-impedance state.
The transfer clock transmits and receives data as is shown in Figure 17.20.
The CSC bit in the UiSMR2 register (i=0 to 4) synchronizes an internally generated clock (internal SCLi)
with the external clock applied to the SCLi pin. When the CSC bit is set to "1" (clock synchronous en-
abled) and the internal SCLi is held high ("H"), the internal SCLi become low ("L") if signal applied to the
SCLi pin is on the falling edge. Value of the UiBRG register is reloaded to start counting for low level. A
counter stops when the SCLi pin is held "L" and then the internal SCLi changes "L" to "H". Counting is
resumed when the SCLi pin become "H". The transfer clock of UARTi is equivalent to the AND for signals
from the internal SCLi and the SCLi pin.
The transfer clock is synchronized between a half cycle before the falling edge of first bit of the internal
SCLi and the rising edge of the ninth bit. Select the internal clock as the transfer clock while the CSC bit
is set to "1".
The SWC bit in the UiSMR2 register determines whether the SCLi pin is fixed to be an "L" signal output on
the falling edge of the ninth cycle of the transfer clock or not.
When the SCLHI bit in the UiSMR4 register is set to "1" (enabled), a SCLi output stops when a stop
condition is detected (high-impedance).
When the SWC2 bit in the UiSMR2 register is set to "1" (0 output), the SCLi pin focibly outputs an "L" signal
while transmitting and receiving. The fixed "L" signal applied to the SCLi pin is cancelled by setting the
SWC2 bit to "0" (transfer clock) and the transfer clock input to and output from the SCLi pin are provided.
When the CKPH bit in the UiSMR3 register is set to "1" and the SWC9 bit in the UiSMR4 register is set to
"1" (SCL "L" hold enabled), the SCLi pin is fixed to be an "L" signal output on the next falling edge after the
ninth bit of the clock. The fixed "L" signal applied to the SCLi pin is cancelled by setting the SWC9 bit to
"0" (SCL "L" hold disabled).
Values output set in bits 7 to 0 (D
from D
Set the default value of SDAi transmit output when the IICM bit is set to "1" (I
SMD0 bits in the UiMR register are set to "000
The DL2 to DL0 bits in the UiSMR3 register determine no delay in the SDAi output or a delay of 2 to 8
UiBRG register count source cycles.
When the SDHI bit in the UiSMR2 register is set to "1" (SDA output disabled), the SDAi pin is forcibly
placed in a high-impedance state. Do not set the SDHI bit on the rising edge of the UARTi transfer clock.
The ABT bit in the UiRB register may be set to "1" (detected).
0
1
4
0
G
3
J
6
u
o r
0 -
. l
7
u
0
1
. The ninth bit (D
p
, 7
0
1
(
2
M
0
3
0
2
5
C
8 /
Page 224
, 4
M
3
2
8
C
) is ACK or NACK.
8 /
f o
4
4
) T
9
5
7
to D
0
) in the UiTB register (i=0 to 4) are provided in descending order
2
" (serial I/O disabled).
17. Serial I/O (Special Function)
2
C mode) and the SMD2 to