M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 170

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
R
R
e
E
3
. v
J
2
Figure 14.1 RLVL Register
0
C
1
9
0 .
8 /
B
0
1
4
0
3
G
J
6
u
o r
0 -
. l
Exit Priority Register
b7
u
NOTES:
0
1
p
, 7
0
b6
1
1. The microcomputer exits stop or wait mode when the requested interrupt priority level is higher than
2. When the FSIT bit is set to "1", an interrupt having the interrupt priority level 7 becomes the high-speed
3. Set the ILVL2 to ILVL0 bits in the interrupt control register after setting the DMAII bit to "1".
4. The DMAII bit becomes indeterminate after reset. To use the DMAII bit for an interrupt setting, set it
(
2
M
Do not change the DMAII bit setting to "0" after setting the DMAII bit to "1". Set the FSIT bit to "0"
0
the level set in the RLVL2 to RLVL0 bits. Set the RLVL2 to RLVL0 bits to the same value as IPL in
the FLG register.
interrupt. In this case, set only one interrupt to the interrupt priority level 7 and the DMAII bit to "0".
when the DMAII bit to "1".
to "0" before setting the interrupt control register.
b5
3
0
2
5
b4
C
8 /
Page 147
b3
, 4
b2
M
3
b1
2
C
b0
f o
8 /
4
4
(b7 - b6)
Symbol
RLVL0
RLVL1
RLVL2
) T
DMAII
9
FSIT
(b4)
Bit
5
Symbol
RLVL
Stop/Wait Mode Exit
Minimum Interrupt Priority
Level Control Bit
High-Speed Interrupt
Set Bit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
DMA II Select Bit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(2)
Bit Name
Address
009F
(1)
16
(4)
b2 b1 b0
0 0 0 : Level 0
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0: Interrupt priority level 7 is used
1: Interrupt priority level 7 is used
0: Interrupt priority level 7 is used
1: Interrupt priority level 7 is used
for normal interrupt
for high-speed interrupt
for interrupt
for DMA II transfer
After Reset
XXXX 0000
Function
2
(3)
RW
RW
RW
RW
RW
RW
14. DMACII

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