M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 148

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
M
R
R
11.8 NMI Interrupt
11.9 Key Input Interrupt
e
E
3
. v
J
2
Figure 11.11 Key Input Interrupt
0
C
The NMI interrupt occurs when a signal applied to the NMI pin changes from a high-level ("H") signal to a
low-level ("L") signal. The NMI interrupt is a non-maskable interrupt. Although the P8
the NMI interrupt input pin, the P8_5 bit in the P8 register indicates the input level for this pin.
NOTES:
Key input interrupt request is generated when one of the signals applied to the P10
mode is on the falling edge. The key input interrupt can be also used as key-on wake-up function to exit wait
or stop mode. To use the key input interrupt, do not use P10
shows a block diagram of the key input interrupt. When an "L" signal is applied to any pins in input mode,
signals applied to other pins are not detected as an interrupt request signal.
When the PSC_7 bit in the PSC register
occurs regardless of interrupt control register settings. When the PSC_7 bit is set to "1", no input from a
port pin is available even when in input mode.
NOTES:
1
9
0 .
8 /
B
1. When the NMI interrupt is not used, connect the NMI pin to V
2. Refer to 24. Programmable I/O Ports about the PSC register.
0
P10
P10
1
P10
4
P10
Pull-up
Transistor
______
______
0
interrupt cannot be ignored, the pin must be connected.
______
3
G
J
6
u
7
6
5
4
o r
/KI
/KI
/KI
0 -
. l
/KI
u
0
1
3
2
1
0
p
, 7
0
1
(
2
M
0
Pull-up
Transistor
0
3
______
Pull-up
Transistor
Pull-up
Transistor
5
2
C
8 /
Page 125
(1)
, 4
M
PSC_7 Bit
3
______
2
C
f o
8 /
4
4
) T
9
5
PD10_7 Bit
PD10_6 Bit
PD10_5 Bit
PD10_4 Bit
PD10_7 Bit
PU31 Bit in PUR3 Register
(2)
is set to "1" (key input interrupt disabled), no key input interrupt
______
______
4
to P10
CC1
via a resistor. Because the NMI
KUPIC Register
Interrupt Control
7
as A/D input ports. Figure 11.11
Circuit
4
to P10
5
/NMI pin is used as
______
7
Key Input
Interrupt
Request
pins in input
11. Interrupts
______