M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 84

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
M
R
R
e
E
3
. v
J
2
0
C
8.1.1 Selecting External Address Bus
8.1.2 Selecting External Data Bus
8.1.3 Selecting Separate/Multiplexed Bus
1
9
8 /
0 .
B
The number of externally-output address buses, the number of chip-select signals and chip-select-as-
signed address space (CS area) vary depending on each external space mode. The PM11 and PM10
bits in the PM1 register determine the external space mode.
The DS register selects either external 8-bit or 16-bit data bus per external space. The data bus in the
external space 3, after reset, becomes 16 bits wide when a low-level ("L") signal is applied to the BYTE
pin and 8 bits wide when a high-level ("H") signal is applied. Keep the BYTE pin input level while the
microcomputer is operating. Internal bus is always 16 bits wide.
The PM05 and PM04 bits in the PM0 register determine either separate or multiplexed bus as bus format.
0
1
4
8.1.3.1 Separate Bus
8.1.3.2 Multiplexed Bus
0
G
The separate bus is a bus format which allows the microcomputer to input and output data and ad-
dress separatelly. The DS register selects 8-bit or 16-bit data bus as the external data bus per exter-
nal space. If all DSi bits in the DS register (i=0 to 3) are set to "0" (8-bit data bus), port P0 becomes the
data bus and port P1, the programmable I/O port. If one of the DSi bits is set to "1" (16-bit data bus),
ports P0 and P1 become the data bus. Port P1 is indeterminate when the microcomputer accesses a
space where the DSi bit is set to "0".
The EWCRi register (i=0 to 3) determines the number of software wait states inserted, when the
microcomputer accesses space using the separate bus.
The multiplexed bus is a bus format which allow the microcomputer to input and output data and
address by timesharing. D
bus. D
controls the data bus width. The EWCRi register (i=0 to 3) controls the number of software wait states
inserted, when the microcomputer accesses a space using the multiplexed bus. Refer to 8.2.4 Bus
Timing for details.
The multiplexed bus can be assigned to access the CS1 area, CS2 area or all CS areas. However,
because the microcomputer starts operation using the separate bus after reset, the multiplexed bus
cannot be assigned to access all CS areas in microprocessor mode. When the PM05 and PM04 bits
in the PM0 register are set to "11
A
3
J
6
u
15
o r
0 -
. l
, of an address are output. See Table 8.2 for details.
u
0
1
p
, 7
0
1
(
0
2
M
0
to D
3
0
2
5
C
15
8 /
Page 61
, 4
are multiplexed with A
M
3
_____
2
C
8 /
f o
4
4
0
) T
9
to D
5
7
_____
2
" (access all CS areas with the bus), 16 low-order bits, from A
are multiplexed with A
0
to A
15
in space accessed by the 16-bit data bus. The DSi bit
_____
_______
0
to A
7
_______
in space accessed by the 8-bit data
_____
8. Bus
0
to