M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 395

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
M
R
R
24. Programmable I/O Ports
24.1 Port Pi Direction Register (PDi Register, i=0 to 15)
24.2 Port Pi Register (Pi Register, i=0 to 15)
24.3 Function Select Register Aj (PSj Register) (j=0 to 3, 5, 8, 9)
24.4 Function Select Register B0 to B3 (PSL0 to PSL3 Registers)
e
E
3
. v
J
2
0
C
87 programmable I/O ports from P0 to P10 (excluding P8
programmable I/O ports from P0 to P15 (excluding P8
determine each port status, input or output. The pull-up control registers determine whether the ports,
divided into groups of four ports, are pulled up or not. P8
allowed. The P8_5 bit in the P8 register indicates an NMI input level since P8
Figures 24.1 to 24.4 show programmable I/O port configurations.
Each pin functions as the programmable I/O port, an I/O pin for internal peripheral functions or the bus
control pin.
To use the pins as input or output pins for internal peripheral functions, refer to the explanations for each
fuction. Refer to 8. Bus when used as the bus control pin.
The registers associated with the programmable I/O ports are as follows.
Figure 24.5 shows the PDi register.
The PDi register selects input or output status of a programmable I/O port. Each bit in the PDi register
corresponds to a port.
In memory expansion and microprocessor mode, the PDi register cannot control pins being used as bus
control pins (A
ALE, HOLD, ALE and RDY). No bit controlling P8
Figure 24.6 shows the Pi register.
The Pi register writes and reads data to communicate with external devices. The Pi register consists of a
port latch to hold output data and a circuit to read pin states. Each bit in the Pi register corresponds to a port.
In memory expansion and microprocessor mode, the Pi register cannot control pins being used as bus
control pins (A
ALE, HOLD, ALE and RDY).
Figures 24.7 to 24.10 show the PSj registers.
The PSj register selects either I/O port or peripheral function output if an I/O port shares pins with a periph-
eral function output (excluding DA0 and DA1.)
When multiple peripheral function outputs are assigned to a pin, set the PSL0 to PSL3, PSC, PSC2, PSC3
and PSD1 registers to select which function is used.
Tables 24.3 to 24.10 list peripheral function output control settings for each pin.
Figures 24.11 and 24.12 show the PSL0 to PSL3 registers.
When multiple peripheral function outputs are assigned to a pin, the PSL0 to PSL3 registers select which
peripheral function output is used.
Refer to 24.10 Analog Input and Other Peripheral Function Input for the PSL3_6 to PSL3_3 bits in the
PSL3 register.
1
9
0 .
8 /
B
0
1
4
0
3
G
J
_________
_________
6
u
o r
0 -
. l
u
0
1
p
, 7
0
1
(
2
M
0
0
0
3
0
to A
to A
2
5
C
8 /
Page 372
22
22
, 4
, A
, A
_______
_______
_____
_____
M
23
23
3
2
, D
, D
C
0
0
f o
8 /
to D
to D
4
4
) T
9
5
15
15
, CS0 to CS3, WRL/WR, WRH/BHE, RD, BCLK/ALE/CLK
, CS0 to CS3, WRL/WR, WRH/BHE, RD, BCLK/ALE/CLK
_______
_______
_______
_______
5
is provided in the direction registers.
_______
_______
______
5
) are in the 144-pin package. The direction registers
_____
_____
5
5
) are available in the 100-pin package and 123
is an input port and no pull-up for this port is
________ _______
________ _______
_____
_____
5
shares pins with NMI.
24. Programmable I/O Ports
OUT
OUT
______
, HLDA/
, HLDA/
_________
_________