MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 965

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC561MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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23.6.11 I-Bus Support Control Register (ICTRL)
If the processor aborts a fetch of the target of a direct branch (due to an exception), the target is not always
visible on the external pins. Program trace is not affected by this phenomenon.
Freescale Semiconductor
1
SRESET
SRESET
12:13
14:15
16:17
18:19
Bits
9:11
Changing the instruction show cycle programming starts to take effect only from the second instruction after the
actual mtspr to ICTRL.
0:2
3:5
6:8
Field
Field IWP2
Addr
Mnemonic
MSB
16
0
IWP0
IWP2
IWP3
CTC
CTD
CTB
CTA
W1
CTA
1
1
7
IWP3
18
2
Compare type of comparator A
Compare type of comparator B
Compare type of comparator C
Compare type of comparator D
I-bus 1st watchpoint
programming
I-bus 2nd watchpoint
programming
I-bus 3rd watchpoint
programming
I-bus 4th watchpoint
programming
3
1
9
Figure 23-24. I-Bus Support Control Register (ICTRL)
SIWP0
EN
20
4
CTB
MPC561/MPC563 Reference Manual, Rev. 1.2
Description
SIWP1
Table 23-26. ICTRL Bit Descriptions
EN
21
5
SIWP2
EN
22
6
0000_0000_0000_0000
0000_0000_0000_0000
SIWP3
CTC
EN
23
7
0xx = not active (reset value)
100 = equal
101 = less than
110 = greater than
111 = not equal
0x = not active (reset value)
10 = match from comparator A
11 = match from comparators (A&B)
0x = not active (reset value)
10 = match from comparator B
11 = match from comparators (A | B)
0x = not active (reset value)
10 = match from comparator C
11 = match from comparators (C&D)
0x = not active (reset value)
10 = match from comparator D
11 = match from comparators (C | D)
0x = not active (reset value)
10 = match from comparator D
11 = match from comparators (C | D)
SPR 158
Non-compressed mode
DIWP0
EN
24
8
DIWP1
EN
25
9
DIWP2
CTD
EN
10
26
Function
1
DIWP3
1xx = not active
000 = equal (reset value)
001 = less than
010 = greater than
011 = not equal
EN
11
27
Compressed Mode
IFM ISCT_SER
12
28
IWP0
Development Support
13
29
14
30
IWP1
LSB
2
15
31
1
23-51

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