MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 120

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC561MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Signal Descriptions
2.3
Bits in the PDMCR (which resides in the SIU memory map) control the slew rate and weak
pull-up/pull-down characteristics of some signals; refer to
PORESET/TRST signal resets all the PDMCR bits asynchronously.
Table 2-5
2-22
HRESET
HRESET
Bits
0:5
Field
Field
Addr
Pad Module Configuration Register (PDMCR)
contains bit descriptions for the PDMCR.
SLRC[0:5]
MSB
Name
16
0
17
1
SLRC0 controls the slew rate of signals on the following modules: TPU3, QADC64E, SGPIOA,
SGPIOD, SGPIOC. For the slew rate refer to
0 Slew rate controlled
1 Not slew rate controlled
SLRC1 controls the slew rate of signals on the following modules: QSPI, TouCAN_A, TouCAN_B.
For the slew rate refer to
0 Slew rate controlled
1 Not slew rate controlled
SLRC2 controls the slew rate of signals on the QSCI in QSMCM . For the slew rate refer to
Appendix F, “Electrical
0 Slew rate controlled
1 Not slew rate controlled
SLRC3 controls the slew rate of signals on the following modules: MIOS14 except
MPWM2/PPM_TX1 and MPWM3 signal. For the slew rate refer to
Characteristics.”
0 Slew rate controlled
1 Not slew rate controlled
SLRC4 controls the slew rate of the MIOS14 MPWM2 signal. For the slew rate refer to
“Electrical
0 Slew rate controlled
1 Not slew rate controlled
SLRC5 controls the slew rate of the MIOS14 MPWM3 signal. For the slew rate refer to
“Electrical
0 Slew rate controlled
1 Not slew rate controlled
18
Figure 2-2. Pads Module Configuration Register (PDMCR)
SLRC
2
19
3
Characteristics.”
Characteristics.”
MPC561/MPC563 Reference Manual, Rev. 1.2
20
4
Table 2-5. PDMCR Field Descriptions
21
5
Characteristics.”
Appendix F, “Electrical
PRDS SPRDS T2CLK_PU
22
6
0000_0000_0000_0000
0000_0000_0000_0000
0x2F C03C
23
7
Description
Appendix F, “Electrical
Appendix F, “Electrical
Characteristics.”
24
8
25
9
10
26
Appendix F, “Electrical
Characteristics.”
PULL_DIS
11
27
Characteristics.” The
12
28
Freescale Semiconductor
13
29
Appendix F,
Appendix F,
14
30
LSB
15
31

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