MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1097
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
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A.2.9.2
This MPC562/MPC564 instruction is compressed into a single segment. The vocabulary table pointer
points to an offset in tables of all RAMs (DECRAMs).
The definition of the class includes:
Data brought from RAM#1 is the 16 MSBs of the decompressed instruction and data brought from
RAM#2 is the 16 LSBs of the decompressed instruction.
A.2.9.3
This MPC562/MPC564 instruction is divided into two segments. Each segment is compressed and mapped
into a different vocabulary. The vocabularies reside in different RAMs. Proper programming can swap the
vocabularies’ locations.
The definition of the class includes:
Freescale Semiconductor
MSB
MSB
•
•
•
•
Alternative #1 (CLASS_2a)
Alternative #2 (CLASS_2b)
16-bit segment #1 – to be compressed
4-bit class
4-bit class
4-bit class
TP1 length = 2-9
TP2 length = 0
TP1 base address, TP2 base address = the two tables’ base addresses for RAM #1 and RAM #2,
respectively.
AS, DS=0
Single Segment Full Compression – CLASS_1
Twin Segment Full Compression – CLASS_2
2- to 9-bit TP1 for segment #1
2- to 9-bit TP1 for segment #2
32-bit segment – to be compressed
2-to 9-bit TP1
Figure A-7. CLASS_1 Instruction Layout
Figure A-8. CLASS_2 Instruction Layout
MPC561/MPC563 Reference Manual, Rev. 1.2
Uncompressed Instruction
Uncompressed Instruction
Compressed Instruction
Compressed Instruction
16-bit segment #2 – to be compressed
2- to 9-bit TP2 for segment #2
2- to 9-bit TP2 for segment #1
MPC562/MPC564 Compression Features
A-9
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