MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 531
![IC MPU 32BIT 56MHZ PPC 388-PBGA](/photos/12/22/122270/mpc561mzp56_sml.jpg)
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Port A signals are configured as inputs or outputs by programming the port data direction register,
DDRQA. The digital input signal states are read from the port data register, PORTQA, when the port data
direction register specifies that the signals are inputs. The digital data in the port data register is driven onto
the port A signals when the corresponding bit in the port data direction register specifies that the signals
are outputs. Refer to
configured as push-pull drivers, external pull-up provisions are not necessary when the output is used to
drive another integrated circuit.
13.7.2
The QADC64E uses two external trigger signals (ETRIG[2:1]). Each of the two input external trigger
signals is associated with one of the scan queues, queue 1 or queue 2 The assignment of ETRIG[2:1] to a
queue is made in the QACR0 register by the TRG bit. When TRG=0, ETRIG[1] triggers queue 1 and
ETRIG[2] triggers queue 2. When TRG=1, ETRIG[1] triggers queue 2 and ETRIG[2] triggers queue 1.
13.7.3
V
power is required to isolate the sensitive analog circuitry from the normal levels of noise present on the
digital power supply. Refer to
The analog supply signals (V
V
Freescale Semiconductor
DDA
RL
) and of the analog multiplexer inputs.
and V
External Trigger Input Signals
Analog Power Signals
SSA
The ETRIG[2:1] pins on the MPC561/MPC563 are multiplexed with the
PCS[7:6] pins.
signals supply power to the analog subsystems of the QADC64E module. Dedicated
Appendix B, “Internal Memory
DDA
Appendix F, “Electrical
MPC561/MPC563 Reference Manual, Rev. 1.2
and V
SSA
) define the limits of the analog reference voltages (V
Figure 13-49
NOTE
Map,” for more information. Since the outputs are
Characteristics,” for more information.
is a diagram of the analog input circuitry.
QADC64E Legacy Mode Operation
RH
and
13-67
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