MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 828

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC561MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Peripheral Pin Multiplexing (PPM) Module
18.4.11
SHORT_CH_REG allows the shorting of transmit channels from the PPM using the bit field SHORT[7:0].
The PPM normally transmits data by right-shifting TX_DATA at the rate of one bit per PPM_TCLK cycle,
TX_DATA15 first. Shorts can be enabled for transmit data bits TX_DATA[1, 3, 5, 7, 9, 11, 13, and 15].
Where a short is enabled for any of these transmit data bits, that bit will be transmitted for two PPM_TCLK
cycles, during its own bit time and the bit time of the following transmit data bit.
18-22
SH_TPU1
1
1
1
1
0
Short Channels Register (SHORT_CH_REG)
If SHORT_CHx = 1, transmit TX_DATAx during TX_DATAx bit time and
repeat TX_DATAx during TX_DATA[x-1] bit time.
MPC561/MPC563
A_TPUCH1
Output
Output
Input
Input
TPU_B
TPU_A
X
Table 18-9. SHORT_REG[SH_TPU] Bit Settings
Figure 18-25. Short Between TPU Channels
MPC561/MPC563 Reference Manual, Rev. 1.2
B_TPUCH1
A_CH
B_CH
Output
Output
Input
Input
X
Data on pad A_TPUCH1 will be the input to A_TPUCH1 and
B_TPUCH1
Output data on B_TPUCH1 will be the input to A_TPUCH1
Output on A_TPUCH1 will be the input data to B_TPUCH1
No Short
No Short
EXAMPLE
Pad
Pad
Effect on TPU3 Modules
B_TPUCH
A_TPUCH
Freescale Semiconductor

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