MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 959

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

23.6.5
Note: COUNTA[16:31] are cleared following reset; COUNTA[0:15] are unaffected by reset.
Freescale Semiconductor
SRESET
SRESET
16:29
30:31
Bits
0:15
Field
Field
Addr
Breakpoint Counter A Value and Control Register
MSB
16
0
Name
CNTV
CNTC
—
Figure 23-18. Breakpoint Counter A Value and Control Register (COUNTA)
Table 23-20. Breakpoint Counter A Value and Control Register (COUNTA)
Bits
17
29
30
31
1
Counter preset value
Reserved
Counter source select
00 not active (reset value)
01 I-bus first watchpoint
10 L-bus first watchpoint
11 Reserved
18
2
EBRKE
IBRKE
Name
DPIE
Table 23-19. DER Bit Descriptions (continued)
19
3
MPC561/MPC563 Reference Manual, Rev. 1.2
20
4
Instruction breakpoint interrupt enable bit.
0 Debug mode entry disabled
1 Debug mode entry enabled (reset value)
External breakpoint interrupt enable bit (development port,
internal or external modules).
0 Debug mode entry disabled
1 Debug mode entry enabled (reset value)
Development port interrupt enable bit
0 Debug mode entry disabled
1 Debug mode entry enabled (reset value)
21
5
0000_0000_0000_0000
22
6
—
Unaffected
SPR 150
23
7
CNTV
Description
Description
24
8
25
9
10
26
11
27
12
28
13
29
Development Support
14
30
CNTC
LSB
15
31
23-45