MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 449

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

For these registers a bus cycle will be performed on the L-bus and the U-bus with the address as shown in
Table
11.8.1
The L2U registers are accessible from the U-bus side only if it is a supervisor mode data access and the
register address is correct and it is indicated on the U-bus that it is a PPC register access.
A user mode access, or an access marked as instruction, to L2U registers from the U-bus side will cause a
data error on the U-bus.
11.8.2
All L2U registers are defined by MPC500 architecture as being 32-bit registers in normal mode. There is
no MPC500 instruction to access either a half word or a byte of the special purpose register.
All L2U registers are only word accessible (read and write) in peripheral mode. A half-word or byte access
in peripheral mode will result in a word transaction.
11.8.3
The L2U module configuration register (L2U_MCR) is used to control the L2U module operation.
Freescale Semiconductor
.
1
L2U_GRA
L2U_RA2
L2U_RA3
When EMCR[CONT] = 0, for external master access only.
11-6.
Name
U-Bus Access
Transaction Size
L2U Module Configuration Register (L2U_MCR)
SPR #
826
827
536
SPR[5:9]
11001
11001
10000
Table 11-5. L2U (PPC) Register Decode (continued)
A[0:17]
Table 11-6. Hex Address For SPR Cycles
MPC561/MPC563 Reference Manual, Rev. 1.2
0
SPR[0:4]
11010
11011
11000
External Master
A[18:22]
spr[5:9]
0x0000_3590
0x0000_3790
0x0000_3100
Address for
Access
1
A[23:27]
spr[0:4]
Access
SUPR
SUPR
SUPR
A[28:31]
0
Region Attribute Register 2
Region Attribute Register 3
Global Region Attribute
L-Bus to U-Bus Interface (L2U)
Description
11-13