MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1091

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

A 4-bit class identifier is added to the beginning of each compressed instruction to supply class
identification during decompression. Compressed and bypass field lengths may vary. (A fully bypassed
instruction, including its 4-bit class identifier, is 36 bits.)
The compressed instruction is guaranteed to start on an even bit. Thus, four bits are needed to find the
starting location of the instruction inside a memory word. The instruction address in decompression on
mode consists of a 28-bit word address (1 Gbyte of address space) and a 4-bit instruction pointer (IP). See
Figure
Freescale Semiconductor
3. Compression of one of the instruction’s halves into a vocabulary pointer and bypass of the other
4. Bypass of the whole instruction. No compression is permitted.
A-2.
half. A bypassed field is one for which non-compressed data (16-bit halfword or 32-bit word) is
placed in the compressed code. After compression is defined, the non-compressed data field is
defined in the class.
4.
1.
3.
2.
Legend
Uncompressed Instruction
Figure A-1. Instruction Compression Alternatives
MPC561/MPC563 Reference Manual, Rev. 1.2
Uncompressed or Bypassed Code
Compressed Code
Class Identifier
4.
1.
3.
2.
OR
Compressed Instruction
MPC562/MPC564 Compression Features
A-3