MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1003
![IC MPU 32BIT 56MHZ PPC 388-PBGA](/photos/12/22/122270/mpc561mzp56_sml.jpg)
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
HRESET
(Tool drives)
RSTI
(Tool drives)
MSEO
EVTI
(Tool drives)
MDO
MSEI
MDI
Device sends out
DID message after
negation of RSTI
Tool sends in DC message with
desired program trace mode enabled.
(BDM can also be enabled through.
DC register configuration. See note.)
Do not send an input message
until at least 2 MCKI after READI is
enabled, or wait until the DID message
is received from the READI module.
NOTE:
If background debug mode (BDM) is enabled,
the ICTRL register cannot be modified through
user program. This register can only be accessed
through the development port.
1
EVTI must be asserted
4 system clocks prior to the
READI module.
negation of RSTI to enable
2
MPC561/MPC563 Reference Manual, Rev. 1.2
DID Message
TCODE=1
3
DC Message
TCODE=18
After the HRESET negation,
the device will start executing
the reset instruction sequence
user program. In this user program,
set the ISCTL field = 0b01 in the
ICTRL register. Also the USIU
should be programmed to ignore
instruction showcycles to avoid
impacting U-bus performance.
Device Ready
TCODE=16
4
16 clocks after receiving
Tool negates HRESET
device ready message.
READI Module
24-35
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