MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1416

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

SCI Control Register 1 (SCCR1) 15-46
SCI Status Register (SCSR) 15-45
SCK 15-12
S-clock 16-8
SCSR 15-48
SE bit 3-21
SEE 23-42
Send break (SBK) 15-48
Sequencer, instruction 3-3
Serial
Serial Clock (SCK) 15-12
Serialization
Service
SGLR 19-22
SGPIOCR 6-48
SGPIODT1 6-46
SGPIODT2 6-47
shadow row
show cycles
SIEL 6-35
Signals
SIMASK 6-33
SIMASK2 6-34
SIMASK3 6-35
Simplified mnemonics 3-33
Single-step trace enable 3-21
SIPEND 6-32
SIPEND2 6-32
SIPEND3 6-33
SISR2 6-37
SISR3 6-37
SIU interrupt pending registers (SIPEND) 6-32
SIU signals, 9-4
SIUMCR 6-25
SIVEC 6-35
Index-16
actual delay before SCK (equation) 15-36
baud rate (equation) 15-35
clock baud rate (SPBR) 15-18
communication interface (SCI) 15-42
formats 15-52
mode (M) bit 15-52
shifter 15-54
fetch 23-1
request breakpoint flag (SRBK) 19-14
erasing 21-28
programming 21-24
select read 21-21
UC3F 21-15
L-bus 11-9
internal clock 8-7
MPC561/563 signals 2-3
multiplexing 2-20
,
15-34
,
15-39
,
15-54
MPC561/MPC563 Reference Manual, Rev. 1.2
SIW0EN 23-52
SIW1EN 23-52
SIW2EN 23-52
SIW3EN 23-52
Slave Select (SS) 15-42
Slave select signal (SS) 15-39
sleep 6-23
SLW0EN 23-50
SLW1EN 23-50
snooping
snooping external bus activity, 3-43
SO bit 3-18
SOF 16-10
soft reset 7-2
Soft reset control field (SOFT_RST) 19-20
SOFT_RST 19-20
SOFTRST 16-12
Software initiated
Software trap enable selection 23-52
software watchdog timer 6-21
SPBR 15-18
SPCR0 15-17
SPCR1 15-19
SPCR2 15-20
SPCR3 15-20
SPE 15-19
special purpose registers 5-6
special purpose registers, general 3-24
SPI
SPIF 15-22
SPIFIE 15-20
SPRG0–SPRG3 3-24
SPRGs 3-24
SPRs 5-6
SPSR 15-20
SPWM D-48
SRAM
SRBK 19-14
SRESET 7-2
SRR field 16-6
SRR0 3-23
SRR1 3-23
L2U 11-9
continuous-scan mode 13-45
single-scan mode 13-42
BBC 4-17
implementation-specific 3-25
finished interrupt enable (SPIFIE) 15-20
BBC 4-17
general 3-24
supervisor space only 15-9
3-56
,
3-57
,
,
,
15-42
,
3-45
3-45
15-42
,
3-59
,
,
,
,
A-17
A-17
A-17
A-17
,
,
3-47
3-47
,
3-60
,
,
3-55
3-49
,
14-43
,
,
3-56
3-50
,
14-46
Freescale Semiconductor
,
,
3-57
3-52
,
A-17
,
,
3-59
3-53
,
,
3-60
3-54
,
3-55
,