MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1401

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

A
Accesses
ACKERR 16-34
Acknowledge error (ACKERR) 16-34
ADDR[8:31] 9-4
Address
address bus 9-37
Address space 13-11
address type (AT[0:3]), 9-38
ALE 23-42
ALEE 23-44
Alignment exception 3-49
ALU–BFU 3-5
AN 13-7
Analog
arbitration, 9-32
AT[0:3] 9-4
atomic 9-32
atomic operation
atomic update primitives, 3-43
B
BAR 3-60
Base ID mask bits 16-32
Baud
BB 9-7
BBCMCR 4-19
BDIP, 9-5
BE bit 3-21
Freescale Semiconductor
clock requirements 13-52
-mark wakeup 15-59
front-end multiplexer 13-36
input
power pins 13-67
reference pins 13-71
section contents 13-2
submodule block diagram 13-34
supply
to digital converter operation 13-34
reservation of data 11-7
clock 15-52
considerations 13-73
pins 13-71
filtering and grounding 13-69
pins 13-67
,
14-6
,
23-53
,
,
14-70
14-66
,
9-37
,
14-66
,
,
14-70
14-2
,
,
16-33
14-71
,
14-51
,
14-37
,
,
14-67
14-36
,
MPC561/MPC563 Reference Manual, Rev. 1.2
14-36
Index
Beginning of queue 2 (BQ2) 13-19
BG 9-7
BI 9-7
Binary
Bit stuff error (STUFFERR) 16-34
BITERR 16-34
BITS 15-18
Bits per transfer
BITSE 15-24
Bit-time 15-51
BIU 13-2
BIUSM
BKPT (TPU asserted) 19-14
BLC 19-12
block diagram
block diagrams
BOFFINT 16-35
Boundary conditions 13-40
boundary scan register 25-4
divider 13-47
-weighted capacitors 13-36
enable (BITSE) 15-24
field (BITS) 15-18
BIUTEST — BIUSM test configuration register 17-13
selecting the time base bus 17-13
CALRAM 22-2
DPTRAM 20-2
JTAG test logic 25-3
L2U 11-2
memory controller 10-2
MIOS 17-1
MPC561/MPC563 1-2
READI 24-3
READI signal interface 24-22
TouCAN 16-1
UC3F EEPROM 21-1
UIMB 12-2
USIU 6-3
analog subsystem 13-34
BBC module 4-2
clock 8-2
DECRAM interfaces 4-13
MPC561/MPC563 signals 2-2
RCPU 3-1
USIU 5-2
,
9-40
,
13-51
,
15-39
,
,
14-48
14-2
,
14-51
,
14-41
,
14-37
,
14-20
Index-1