MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 112

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Signal Descriptions
2-14
ALTREF
VDDA
VSSA
PCS0 / SS / QGPIO0
PCS[1:3] / QGPIO[1:3]
MISO / QGPIO4
MOSI / QGPIO5
SCK / QGPIO6
TXD1 / QGPO1
Signal Name
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signals
No. of
1
1
1
1
3
1
1
1
1
MPC561/MPC563 Reference Manual, Rev. 1.2
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
I
I
ALTREF
VDDA
VSSA
QGPIO0
QGPIO[1:3]
QGPIO4
QGPIO5
QGPIO6
QGPO1
Function after
Reset
QSMCM
1
ALTREF. Input signal for alternate reference voltage for the
QADC64E_A and QADC64E_B modules.
VDDA. Power supply input to analog subsystems of the
QADC64E_A and QADC64E_B modules.
VSSA. Ground level for analog subsystems of the
QADC64E_A and QADC64E_B modules.
PCS0. This signal provides QSPI peripheral chip select 0 for
the QSMCM module.
SS. Assertion of this bidirectional signal places the QSPI in
slave mode.
Port QGPIO0. When this signal is not needed for a QSPI
application it can be configured as a general-purpose
input/output.
PCS[1:3]. These signals provide QSPI peripheral chip
selects for the QSMCM module.
Port QGPIO[1:3]. When these signals are not needed for
QSPI applications they can be configured as
general-purpose input/outputs.
Master-In Slave-Out (MISO). This bidirectional signal is the
serial data input to the QSPI in master mode, and serial data
output from the QSPI in slave mode.
Port QGPIO4. When this signal is not needed for a QSPI
application it can be configured as a general-purpose
input/output.
Master-Out Slave-In (MOSI). This bidirectional signal is the
serial data output from the QSPI in master mode and serial
data input to the QSPI in slave mode.
Port QGPIO5. When this signal is not needed for a QSPI
application it can be configured as a general-purpose
input/output.
SCK. This bidirectional signal is the clock from the QSPI in
master mode or is the clock to the QSPI in slave mode.
Port QGPIO6 for the QSMCM module. When this signal is
not needed for a QSPI application it can be configured as a
general-purpose input/output. When the QSPI is enabled for
serial transmitting, the signal cannot function as a GPIO.
Transmit Data 1. This is the serial data output from the SCI1.
Port QGPO 1. When these signals are not needed for SCI
applications, they can be configured as general-purpose
outputs. When the transmit enable bit in the SCI control
register is set to a logic 1, these signals cannot function as
general-purpose outputs.
Description
Freescale Semiconductor