MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 189

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

3.15.3
Storage control instructions mtsr, mtsrin, mfsr, mfsrin, dcbi, tlbie, tlbia, and tlbsync are not implemented
by the MPC561/MPC563.
3.15.4
The following paragraphs define the types of OEA exceptions. The exception table vector defines the
offset value by exception type. Refer to
3.15.4.1
A system reset exception occurs when:
Settings caused by reset as shown in
A non-maskable interrupt (NMI) occurs when the IRQ0 is asserted and the following registers are set.
Freescale Semiconductor
•
•
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Any reset signal is asserted: PORESET, HRESET, or SRESET
An internal reset is requested, such as from the software watchdog timer
MSR
SRR0
SRR1
FPECR
ICTRL
LCTRL1
LCTRL2
COUNTA[16:31]
COUNTB[16:31]
Storage Control Instructions
Exceptions
Register Name
System Reset Exception and NMI (0x0100)
Register
Table 3-23. Register Settings following an NMI
1
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 3-22. Settings Caused by Reset
0x0000 0000
IP depends on internal data bus configuration word; ME is unchanged.
DCMPEN is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP]). All other bits are cleared
Undefined
Undefined
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
Table
10:15
Other
Bits
1:4
Table
All
3-22.
3-19.
Set to the effective address of the next instruction the
processor executes if no interrupt conditions are present
Cleared to 0
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
Setting
Description
Central Processing Unit
3-45