MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 940
![IC MPU 32BIT 56MHZ PPC 388-PBGA](/photos/12/22/122270/mpc561mzp56_sml.jpg)
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Development Support
The processor enters into the debug mode state when at least one of the bits in the exception cause register
(ECR) is set, the corresponding bit in the debug enable register (DER) is enabled and debug mode is
enabled. When debug mode is enabled and an enabled event occurs, the processor waits until its pipeline
is empty and then starts fetching the next instructions from the development port. For information on the
exact value of machine status save/restore registers (SRR0 and SRR1) refer to
“Exceptions.”
When the processor is in debug mode the freeze indication is asserted thus allowing any peripheral that is
programmed to do so to stop. The fact that the CPU is in debug mode is also broadcast to the external world
using the value b11 on the VFLS pins.
The development port should read the value of the exception cause register (ECR) in order to get the cause
of the debug mode entry. Reading the exception cause register (ECR) clears all its bits.
23.3.1.3
The CPU enters the check stop state if the machine check interrupt is disabled (MSR[ME] = 0) and a
machine check interrupt is detected. However, if a machine check interrupt is detected when MSR[ME] =
23-26
•
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•
•
•
•
•
•
•
•
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Implementation specific data protection error
External interrupt, recognized when MSR[EE] = 1
Alignment interrupt
Program interrupt
Floating point unavailable exception
Floating point assist exception
Decrementer exception, recognized when MSR[EE] = 1
System call exception
Trace, asserted when in single trace mode or when in branch trace mode (refer to
“Trace Exception
Implementation dependent software emulation exception
Instruction breakpoint, when breakpoints are masked (BRKNOMSK bit in the LCTRL2 is clear)
recognized only when MSR[RI] = 1, when breakpoints are not masked (BRKNOMSK bit in the
LCTRL2 is set) always recognized
Load/store breakpoint, when breakpoints are masked (BRKNOMSK bit in the LCTRL2 is cleared)
recognized only when MSR[RI] = 1, when breakpoints are not masked (BRKNOMSK bit in the
LCTRL2 is set) always recognized
Peripherals breakpoint, from the development port, internal and external modules. are recognized
only when MSR[RI] = 1.
Development port non-maskable interrupt, as a result of a debug station request. Useful in some
catastrophic events like an endless loop when MSR[RI] = 0. As a result of this event the machine
may enter a non-restartable state, for more information refer to
Check Stop State and Debug Mode
The freeze signal can be asserted by software when debug mode is disabled.
(0x0D00)”)
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
Section 3.13.4,
Section 3.13.4,
Freescale Semiconductor
Section 3.15.4.11,
“Exceptions.”
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