MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 757
![IC MPU 32BIT 56MHZ PPC 388-PBGA](/photos/12/22/122270/mpc561mzp56_sml.jpg)
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
Bits
8:15
5:6
0
1
2
3
4
7
EDGN
EDGN
EDGP
Name
FREN
PINC
PINL
CLS
CP
—
1
1
0
0
CLS
11
10
01
00
Clock input signal status bit — This read-only status bit reflects the logic state of the clock input
signal MMCnC (MDA11, MDA13, MDA27, MDA30, PWM16, and PWM18).
Modulus load input signal status bit — This read-only status bit reflects the logic state of the
modulus load signal MMCnL (MDA12, MDA14, MDA28, MDA31, PWM17, and PWM19).
Freeze enable — This active high read/write control bit enables the MMCSM to recognize the
MIOB freeze signal.
Modulus load falling-edge sensitivity — This active high read/write control bit sets falling-edge
sensitivity for the MMCnL signal, such that a high-to-low transition causes a load of the
MMCSMCNT.
Modulus load rising-edge sensitivity
This active high read/write control bit sets rising-edge sensitivity for the MMCnL signal, such that
a low-to-high transition causes a load of the MMCSMCNT.
See
Clock select — These read/write control bits select the clock source for the modulus counter.
Either the rising edge or falling edge of the clock signal on the MMCnC signal may be selected,
as well as, the internal MMCSM prescaler output or disable mode (no clock source). See
Table 17-14
Reserved
Clock prescaler — This 8-bit data field is also accessible as an 8-bit data register. It stores the
two’s complement of the modulus value to be loaded into the built-in 8-bit clock prescaler. The
new value is loaded into the prescaler counter on the next counter overflow, or upon setting the
CLS1 — CLS0 bits for selecting the clock prescaler as the clock source.
Table 17-15
EDGP
Table 17-13
1
0
1
0
Table 17-12. MMCSMSCR Bit Descriptions
Table 17-13. MMCSMCNT Edge Sensitivity
for details about the clock selection.
gives the clock divide ratio according to the value of CP.
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 17-14. MMCSMCNT Clock Signal
MMCSMCNT load on rising and falling edges
MMCSMCNT load on falling edges
MMCSMCNT load on rising edges
None (disabled)
for details about edge sensitivity.
MMCSM clock prescaler
Clock signal falling-edge
Clock signal rising-edge
Clocking Selected
None (disable)
Description
Edge Sensitivity
Modular Input/Output Subsystem (MIOS14)
17-25
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