MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 134

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Signal Descriptions
2-36
HRESET
SRESET
Signal List
RSTCONF /
PORESET/
TEXP
WE[0:3]
BE[0:3]
CS[0:3]
TEA
AT[0:3]
TRST
BI
TA
STS
OE
7, 12
7, 12
7, 12
7, 11
7
7
11
11, 12
11, 12
/
7
7
7
7
/
/
1
Voltage
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
2.6 V
Table 2-14. MPC561/MPC563 Signal Reset State (continued)
13
13
Controlled
Slew Rate
Option?
MPC561/MPC563 Reference Manual, Rev. 1.2
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
50 ; 25
Development and Debug
Drive
Load
(pF)
N/A
NA
NA
2
System Control
PU2.6 when
driver not
enabled or until
SPRDS is set
PU2.6 when
driver not
enabled or until
SPRDS is set
PU2.6 until reset
negates
PU2.6 when
driver not
enabled or until
SPRDS is set
PU2.6 when
driver not
enabled or until
SPRDS is set.
PU2.6 until reset
negates
PU2.6 when
driver not
enabled or until
SPRDS is set
External pull-up
required
PU2.6 when
driver not
enabled or until
SPRDS is set
External pull-up
required
PU2.6 when
driver not
enabled or until
SPRDS is set
External pull-up
required
Reset State
Hysteresi
Enabled?
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
s
TA
TEA
OE
RSTCONF until reset
negates.
Controlled by DBGC in the
reset configuration word.
See
CS[0:3]
Controlled by bit ATWC (bit
12) of the reset configuration
word. See
PORESET/TRST
HRESET
SRESET
Function After HRESET,
Table
PORESET/TRST
6-8.
Table
Freescale Semiconductor
6-8.