MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 288

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

System Configuration and Protection
6.2.2.5.3
Table 6-26
6-48
1
HRESET
HRESET
22:23
24:31
Bits
8:15
0:7
Field
Field GDDR
16
17
18
19
20
21
Addr
describes the bit values for data direction control.
MSB
SDDRC[0:7]
16
0
0
SGPIO Control Register (SGPIOCR)
GDDR0
GDDR1
GDDR2
GDDR3
GDDR4
GDDR5
SDDRD
[24:31]
Name
—
—
GDDR
17
1
1
Group data direction for SGPIOD[0:7]
Group data direction for SGPIOD[8:15]
SGPIO data direction for SGPIOC[0:7]. Each SDDR bit zero to seven controls the direction
of the corresponding SGPIOC pin zero to seven
Reserved
Group data direction for SGPIOD[16:23]
Group data direction for SGPIOA[8:15]
Group data direction for SGPIOA[16:23]
Group data direction for SGPIOA[24:31]
Reserved
SGPIO data direction for SGPIOD[24:31]. Each SDDRD bits 24:31 controls the direction
of the corresponding SGPIOD pin [24:31].
GDDR
18
Figure 6-43. SGPIO Control Register (SGPIOCR)
2
2
SDDR/GDDR
MPC561/MPC563 Reference Manual, Rev. 1.2
SDDRC[0:7]
Table 6-25. SGPIOCR Bit Descriptions
GDDR
19
Table 6-26. Data Direction Control
3
3
0
1
GDDR
20
4
4
0000_0000_0000_0000
0000_0000_0000_0000
GDDR
SGPIO configured as output
SGPIO configured as input
21
5
5
0x2F C02C
Operation
22
6
Description
—
23
7
24
8
25
9
10
26
SDDRD[24:31]
11
27
—
Freescale Semiconductor
12
28
13
29
14
30
LSB
15
31