MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1411

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Phase buffer segment 1/2 (PSEG1/2) bit field 16-30
phase-lock loop, 9-8
PIE1 13-16
PIE2 13-18
PISCR 6-44
PIT 6-20
PITC 6-45
PITR 6-45
PLL 8-3
PLL, 9-8
PLPRCR 8-33
Pointer 15-16
PORESET 7-1
Port
port size device interfaces (illustration), 9-31
port width definition 9-1
PORTQA 13-13
PORTQB 13-13
PORTQS 15-11
Positive stress 13-76
power on reset 7-1
PPWA D-38
PQA 13-66
PQSPAR 15-10
PR bit 3-7
PRE 23-42
Precise exceptions 3-36
PREE 23-44
Prescaler 13-48
PRESDIV (bit field) 16-30
PRESDIV (register) 16-8
priority
Privilege level 3-7
Processor version register 3-25
Program 3-51
Freescale Semiconductor
loss of lock 7-2
A data register (PORTQA) 13-13
B data register (PORTQB) 13-13
clock
clock high time (PSH) 13-48
control
divide
CALRAM overlay regions 22-11
channel service 19-4
exception 3-51
(PSCK) 19-12
high time (PSH) 13-15
low time (PSL) 13-15
for TCR1 19-5
for TCR2 19-7
factor field 16-30
register (PRESDIV) 16-8
,
,
,
,
3-21
14-17
14-19
14-65
,
15-34
,
3-21
,
14-74
,
15-39
,
16-10
,
16-29
,
14-15
,
16-29
MPC561/MPC563 Reference Manual, Rev. 1.2
Programmable
Programmable time accumulator (PTA) D-3
Propagation segment time (PROPSEG) 16-29
PROPSEG 16-13
PSCK 19-12
PSEG1 16-30
PSEG2 16-10
PSEGS1 16-13
PSH 13-15
PSL 13-15
PT 15-47
PTA D-3
PTR, 9-4
Pulse-width modulation (PWM) D-44
PVR 3-25
PWM D-44
Q
QACR0 13-7
QACR1 13-7
QACR2 13-7
QADC64E conversion queue operation 14-29
QADC64E module configuration register
QADCINT 13-7
QADCMCR 13-7
QADCTEST 13-7
QADMCR 13-8
QASR 13-8
QCLK 13-47
QDDR 15-13
QILR 15-9
QOM D-5
QPAR 15-12
QPDR 15-11
QS 13-24
QSCI1 registers
QSM
channel service priority 19-4
transfer length 15-15
parameters D-3
parameters D-44
frequency 13-47
QSCI1CR 15-59
QSCI1SR 15-59
global registers 15-6
pin function 15-11
QSPI 15-14
registers
(QADCMCR) 13-7
operating modes 15-27
operation 15-25
RAM 15-22
,
,
,
9-38
15-53
14-25
,
,
13-48
13-20
,
,
,
,
,
,
,
15-42
14-48
13-15
13-15
13-17
15-42
16-13
,
,
13-12
,
,
,
16-29
,
D-40
13-8
,
14-15
14-48
14-7
,
,
,
,
14-7
14-7
13-18
16-30
,
,
,
14-11
,
14-8
D-51
14-22
,
14-16
,
14-7
,
14-18
Index-11